clwb
Cache Line Write Back
CLWB m8
Writes back modified cache line without flushing (Persistent Memory).
Details
Cache Line Write Back to memory without invalidation. Writes back a modified cache line to memory (coherent with other agents) but does not invalidate it from the cache hierarchy; optimized for persistent memory workloads. No flags are affected. Serialization and memory ordering depend on surrounding instructions. Requires CLWB capability.
Pseudocode Operation
// Write back cache line containing [m8] to memory
// Cache line remains in cache after writeback
write_back_cache_line(address(m8))Example
CLWB [rbp-1]
Encoding
Binary Layout
66
+0
0F
+1
AE
+2
ModRM
+3
Operands
-
dest
8-bit memory operand
Reference (Intel® SDM)
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| 66 0F AE /6 | CLWB | M | V/V | M | Writes back modified cache line containing m8, and may CLWB m8 retain the line in cache hierarchy in non-modified state. Instruction Operand Encoding1 Op/En Operand 1 Operand 2 Operand 3 Operand 4 ModRM:r/m (w) N/A N/A N/A |
Description
Writes back to memory the cache line (if modified) that contains the linear address specified with the memory operand from any level of the cache hierarchy in the cache coherence domain. The line may be retained in the cache hierarchy in non-modified state. Retaining the line in the cache hierarchy is a performance optimization (treated as a hint by hardware) to reduce the possibility of cache miss on a subsequent access. Hardware may choose to retain the line at any of the levels in the cache hierarchy, and in some cases, may invalidate the line from the cache hierarchy. The source operand is a byte memory location.
The availability of CLWB instruction is indicated by CPUID.07H.00H:EBX.CLWB[24]. The aligned cache line size affected is also indicated by the value in CPUID.01H:EBX[15:8].
The memory attribute of the page containing the affected line has no effect on the behavior of this instruction. It should be noted that processors are free to speculatively fetch and cache data from system memory regions that are assigned a memory-type allowing for speculative reads (such as, the WB, WC, and WT memory types).
PREFETCHh instructions can be used to provide the processor with hints for this speculative behavior. Because this speculative fetching can occur at any time and is not tied to instruction execution, the CLWB instruction is not ordered with respect to PREFETCHh instructions or any of the speculative fetching mechanisms (that is, data can be speculatively loaded into a cache line just before, during, or after the execution of a CLWB instruction that references the cache line).
Executions of the CLWB instruction are ordered with respect to fence instructions and to locked read-modify-write instructions; they are also ordered with respect to older writes to the cache line being written back. They are not ordered with respect to other executions of CLWB, to executions of CLFLUSH and CLFLUSHOPT, or to younger writes to the cache line being written back. Software can use the SFENCE instruction to order an execution of CLWB relative to one of those operations.
For usages that require only writing back modified data from cache lines to memory (do not require the line to be invalidated), and expect to subsequently access the data, software is recommended to use CLWB (with appropriate fencing) instead of CLFLUSH or CLFLUSHOPT for improved performance.
The CLWB instruction can be used at all privilege levels and is subject to all permission checking and faults associated with a byte load. Like a load, the CLWB instruction sets the accessed flag but not the dirty flag in the page tables.
In some implementations, the CLWB instruction may always cause transactional abort with Transactional Synchronization Extensions (TSX). CLWB instruction is not expected to be commonly used inside typical transactional regions. However, programmers must not rely on CLWB instruction to force a transactional abort, since whether they cause transactional abort is implementation dependent.
Operation
Cache_Line_Write_Back(m8); 1. The Mod field of the ModR/M byte cannot have value 11B. CLWB—Cache Line Write Back Vol. 2A 3-154
Flags Affected
None. C/C++ Compiler Intrinsic Equivalent CLWB void _mm_clwb(void const *p);
Exceptions
Protected Mode Exceptions
#UD If the LOCK prefix is used.
If CPUID.07H.00H:EBX.CLWB[24] = 0.
#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
#SS(0) For an illegal address in the SS segment.
#PF(fault-code) For a page fault.
Real-Address Mode Exceptions
#UD If the LOCK prefix is used.
If CPUID.07H.00H:EBX.CLWB[24] = 0.
#GP If any part of the operand lies outside the effective address space from 0 to FFFFH.
Virtual-8086 Mode Exceptions
Same exceptions as in real address mode.
#PF(fault-code) For a page fault.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#UD If the LOCK prefix is used.
If CPUID.07H.00H:EBX.CLWB[24] = 0.
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.
#GP(0) If the memory address is in a non-canonical form.
#PF(fault-code) For a page fault.
CLWB—Cache Line Write Back Vol. 2A 3-155