roundpd
Round Packed Double-Precision
Rounds all packed doubles according to immediate mode.
Pseudocode Operation
rounding_mode ← imm8[2:0]
suppress_inexact ← imm8[3]
for i in 0..1:
f64 ← src[i*64+63:i*64]
if (rounding_mode == 0): /* round to nearest */
result ← round_nearest(f64)
elif (rounding_mode == 1): /* round down */
result ← round_down(f64)
elif (rounding_mode == 2): /* round up */
result ← round_up(f64)
elif (rounding_mode == 3): /* truncate */
result ← truncate(f64)
dest[i*64+63:i*64] ← resultExample
Encoding
Operands
-
dest
128-bit XMM SIMD register -
src1
128-bit XMM SIMD register or Memory operand -
src2
8-bit signed immediate
Related
More in SSE4.1
Reference
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| 66 0F 3A 09 /r ib | ROUNDPD xmm1, xmm2/m128, imm8 | RMI | V/V | SSE4_1 | Round packed double precision floating-point values in xmm2/m128 and place the result in xmm1. The rounding mode is determined by imm8. |
| VEX.128.66.0F3A.WIG 09 /r ib | VROUNDPD xmm1, xmm2/m128, imm8 | RMI | V/V | AVX | Round packed double precision floating-point values in xmm2/m128 and place the result in xmm1. The rounding mode is determined by imm8. |
| VEX.256.66.0F3A.WIG 09 /r ib | VROUNDPD ymm1, ymm2/m256, imm8 | RMI | V/V | AVX | Round packed double precision floating-point values in ymm2/m256 and place the result in ymm1. The rounding mode is determined by imm8. |
Description
Round the 2 double precision floating-point values in the source operand (second operand) using the rounding mode specified in the immediate operand (third operand) and place the results in the destination operand (first operand). The rounding process rounds each input floating-point value to an integer value and returns the integer result as a double precision floating-point value. The immediate operand specifies control fields for the rounding operation, three bit fields are defined and shown in
The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an SNaN then it will be converted to a QNaN. If DAZ is set to ‘1 then denormals will be converted to zero before rounding. 128-bit Legacy SSE version: The second source can be an XMM register or 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding YMM register destination are unmodified. VEX.128 encoded version: the source operand second source operand or a 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding YMM register destination are zeroed. VEX.256 encoded version: The source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register. Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
8 3 2 1 0
Reserved
P - Precision Mask (SPE); 0: normal, 1: inexact RS - Rounding select; 1: MXCSR.RC, 0: Imm8.RC RC - Rounding mode
Table 4-21. Rounding Modes and Encoding of Rounding Control (RC) Field
Rounding RC Field Description
Mode Setting
Round to 00B Rounded result is the closest to the infinitely precise result. If two values are equally close, the result is nearest (even) the even value (i.e., the integer value with the least-significant bit of zero). Round down 01B Rounded result is closest to but no greater than the infinitely precise result.
(toward -∞)
Round up 10B Rounded result is closest to but no less than the infinitely precise result.
(toward +∞) Round toward 11B Rounded result is closest to but no greater in absolute value than the infinitely precise result. zero (Truncate)
Operation
IF (imm[2] = ‘1) THEN // rounding mode is determined by MXCSR.RC DEST[63:0] := ConvertDPFPToInteger_M(SRC[63:0]); DEST[127:64] := ConvertDPFPToInteger_M(SRC[127:64]); ELSE // rounding mode is determined by IMM8.RC DEST[63:0] := ConvertDPFPToInteger_Imm(SRC[63:0]); DEST[127:64] := ConvertDPFPToInteger_Imm(SRC[127:64]); FI ROUNDPD (128-bit Legacy SSE Version) DEST[63:0] := RoundToInteger(SRC[63:0]], ROUND_CONTROL) DEST[127:64] := RoundToInteger(SRC[127:64]], ROUND_CONTROL) DEST[MAXVL-1:128] (Unmodified) VROUNDPD (VEX.128 Encoded Version) DEST[63:0] := RoundToInteger(SRC[63:0]], ROUND_CONTROL) DEST[127:64] := RoundToInteger(SRC[127:64]], ROUND_CONTROL) DEST[MAXVL-1:128] := 0 VROUNDPD (VEX.256 Encoded Version) DEST[63:0] := RoundToInteger(SRC[63:0], ROUND_CONTROL) DEST[127:64] := RoundToInteger(SRC[127:64]], ROUND_CONTROL) DEST[191:128] := RoundToInteger(SRC[191:128]], ROUND_CONTROL) DEST[255:192] := RoundToInteger(SRC[255:192] ], ROUND_CONTROL)
Intel C/C++ Compiler Intrinsic Equivalent
__m128 _mm_round_pd(__m128d s1, int iRoundMode); __m128 _mm_floor_pd(__m128d s1); __m128 _mm_ceil_pd(__m128d s1) __m256 _mm256_round_pd(__m256d s1, int iRoundMode); __m256 _mm256_floor_pd(__m256d s1); __m256 _mm256_ceil_pd(__m256d s1)