xgetbv

Get Value of Extended Control Register

XGETBV

Reads the state of XCR0 (feature mask) into EDX:EAX.

Pseudocode Operation

EDX:EAX ← XCR0

Encoding

Binary Layout

Format Legacy

Opcode NP 0F 01 D0

Extension XSAVE

Operands

Reference

View in Intel® 64 and IA-32 Architectures SDM ↗ Intel® SDM

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
NP 0F 01 D0	XGETBV	ZO	Valid Valid		Reads an XCR specified by ECX into EDX:EAX.

Description

Reads the contents of the extended control register (XCR) specified in the ECX register into registers EDX:EAX. (On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The EDX register is loaded with the high-order 32 bits of the XCR and the EAX register is loaded with the low-order 32 bits. (On processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are cleared.) If fewer than 64 bits are implemented in the XCR being read, the values returned to EDX:EAX in unimplemented bit locations are undefined. XCR0 is supported on any processor that supports the XGETBV instruction. If CPUID.0DH.01H:EAX.XGETBV1[2] = 1, executing XGETBV with ECX = 1 returns in EDX:EAX the logical-AND of XCR0 and the current value of the XINUSE state-component bitmap. This allows software to discover the state of the init optimization used by XSAVEOPT and XSAVES. See Chapter 13, “Managing State Using the XSAVE Feature Set‚” in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1. Use of any other value for ECX results in a general-protection (#GP) exception.

Operation

EDX:EAX := XCR[ECX];

Intel C/C++ Compiler Intrinsic Equivalent

XGETBV unsigned __int64 _xgetbv( unsigned int);

Flags Affected

None.

Exceptions

Protected Mode Exceptions

#GP(0)If an invalid XCR is specified in ECX (includes ECX = 1 if CPUID.0DH.01H:EAX.XGETBV1[2] = 0). #UD If CPUID.01H:ECX[26, “XSAVE”] = 0. If CR4.OSXSAVE[bit 18] = 0. If the LOCK prefix is used.

Real-Address Mode Exceptions