pusha

Push All General-Purpose Registers

PUSHA

Pushes AX, CX, DX, BX, SP, BP, SI, DI (Invalid in 64-bit).

Details

Pushes all eight general-purpose 16-bit or 32-bit registers (AX/EAX, CX/ECX, DX/EDX, BX/EBX, SP/ESP, BP/EBP, SI/ESI, DI/EDI) onto the stack in that order. The SP/ESP value pushed is the value before the first push. This instruction is invalid in 64-bit mode and is primarily a legacy instruction. No flags are affected.

Pseudocode Operation

temp ← SP; SP ← SP - 16; [SP+0] ← AX; [SP+2] ← CX; [SP+4] ← DX; [SP+6] ← BX; [SP+8] ← temp; [SP+10] ← BP; [SP+12] ← SI; [SP+14] ← DI

Example

PUSHA

Encoding

Binary Layout

Format Legacy

Opcode 60

Extension Base (32-bit only)

Operands

Reference (Intel® SDM)

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
60	PUSHA	ZO	Invalid Valid		Push AX, CX, DX, BX, original SP, BP, SI, and DI.
60	PUSHAD	ZO	Invalid Valid		Push EAX, ECX, EDX, EBX, original ESP, EBP, ESI, and EDI.

Description

Pushes the contents of the general-purpose registers onto the stack. The registers are stored on the stack in the following order: EAX, ECX, EDX, EBX, ESP (original value), EBP, ESI, and EDI (if the current operand-size attribute is 32) and AX, CX, DX, BX, SP (original value), BP, SI, and DI (if the operand-size attribute is 16). These instructions perform the reverse operation of the POPA/POPAD instructions. The value pushed for the ESP or SP register is its value before prior to pushing the first register (see the “Operation” section below). The PUSHA (push all) and PUSHAD (push all double) mnemonics reference the same opcode. The PUSHA instruction is intended for use when the operand-size attribute is 16 and the PUSHAD instruction for when the operandsize attribute is 32. Some assemblers may force the operand size to 16 when PUSHA is used and to 32 when PUSHAD is used. Others may treat these mnemonics as synonyms (PUSHA/PUSHAD) and use the current setting of the operand-size attribute to determine the size of values to be pushed from the stack, regardless of the mnemonic used. In the real-address mode, if the ESP or SP register is 1, 3, or 5 when PUSHA/PUSHAD executes: an #SS exception is generated but not delivered (the stack error reported prevents #SS delivery). Next, the processor generates a #DF exception and enters a shutdown state as described in the #DF discussion in Chapter 7 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A. This instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.

Operation

IF 64-bit Mode
THEN #UD
FI;
IF OperandSize = 32 (* PUSHAD instruction *)
THEN
Temp := (ESP);
Push(EAX);
Push(ECX);
Push(EDX);
Push(EBX);
Push(Temp);
Push(EBP);
Push(ESI);
Push(EDI);
ELSE (* OperandSize = 16, PUSHA instruction *)
Temp := (SP);
Push(AX);
Push(CX);
Push(DX);
Push(BX);
Push(Temp);


PUSHA/PUSHAD—Push All General-Purpose Registers                                                                                          Vol. 2B 4-526
Push(BP);
Push(SI);
Push(DI);
FI;

Flags Affected

None.

Exceptions

Protected Mode Exceptions

#SS(0) If the starting or ending stack address is outside the stack segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If an unaligned memory reference is made while the current privilege level is 3 and alignment checking is enabled. #UD If the LOCK prefix is used.

Real-Address Mode Exceptions

#GP If the ESP or SP register contains 7, 9, 11, 13, or 15. #UD If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

#GP(0) If the ESP or SP register contains 7, 9, 11, 13, or 15. #PF(fault-code) If a page fault occurs. #AC(0) If an unaligned memory reference is made while alignment checking is enabled. #UD If the LOCK prefix is used.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#UD If in 64-bit mode. PUSHA/PUSHAD—Push All General-Purpose Registers Vol. 2B 4-527