xabort

Transaction Abort

XABORT imm8

Forces an RTM abort.

Pseudocode Operation

if (RTM_TransactionActive) {
  // Abort transaction
  EAX[7:0] ← imm8;
  RTM_TransactionActive ← 0;
  RIP ← XBEGINFallbackAddress;  // Branch to XBEGIN offset
} else {
  // Outside transaction; XABORT is a no-op
}

Example

XABORT 3

Encoding

Binary Layout

C6

+0

F8

+1

 

Format Legacy

Opcode C6 F8

Extension RTM (TSX)

Operands

• dest
  8-bit signed immediate

Related

More in RTM (TSX)

Reference

View in Intel® 64 and IA-32 Architectures SDM ↗ Intel® SDM

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
C6 F8 ib	XABORT imm8	A	V/V	RTM	Causes an RTM abort if in RTM execution.

Instruction Operand Encoding

Op/En	Operand 1	Operand 2	Operand 3	Operand 4
A	imm8	N/A	N/A	N/A

Description

XABORT forces an RTM abort. Following an RTM abort, the logical processor resumes execution at the fallback address computed through the outermost XBEGIN instruction. The EAX register is updated to reflect an XABORT instruction caused the abort, and the imm8 argument will be provided in bits 31:24 of EAX.

Operation

XABORT
IF RTM_ACTIVE = 0
THEN
Treat as NOP;
ELSE
GOTO RTM_ABORT_PROCESSING;
FI;

(* For any RTM abort condition encountered during RTM execution *)
RTM_ABORT_PROCESSING:
Restore architectural register state;
Discard memory updates performed in transaction;
Update EAX with status and XABORT argument;
RTM_NEST_COUNT:= 0;
RTM_ACTIVE:= 0;
SUSLDTRK_ACTIVE := 0;
IF 64-bit Mode
THEN
RIP:= fallbackRIP;
ELSE
EIP := fallbackEIP;
FI;
END

Intel C/C++ Compiler Intrinsic Equivalent

XABORT void _xabort( unsigned int);

Flags Affected

None.

Exceptions

SIMD Floating-Point Exceptions

None. XABORT-Transactional Abort Vol. 2D 6-20

Other Exceptions

#UDCPUID.07H.00H:EBX.RTM[11] = 0. If LOCK prefix is used. XABORT-Transactional Abort Vol. 2D 6-21