mulss

Multiply Scalar Single-Precision

MULSS xmm1, xmm2/m32

Multiplies the low single-precision floating-point value.

Details

Multiplies the low 32-bit single-precision floating-point value in the source by the destination XMM register, following IEEE 754 semantics. The high 96 bits of the destination XMM register are left unchanged. The result may raise floating-point exceptions (invalid operation, overflow, underflow, inexact) but does not modify the general-purpose arithmetic flags (OF, SF, ZF, AF, CF, PF). This is an SSE instruction available in 32-bit and 64-bit modes.

Pseudocode Operation

xmm1[31:0] ← xmm1[31:0] * src[31:0] (IEEE 754 single-precision)
xmm1[127:32] ← unchanged
FP_exceptions may be raised

Example

MULSS xmm1, xmm2/m32

Encoding

Binary Layout
F3
+0
0F
+1
59
+2
 
Format SSE
Opcode F3 0F 59
Extension SSE

Operands

  • dest
    128-bit XMM SIMD register
  • src
    128-bit XMM SIMD register or Memory operand

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
F3 0F 59 /r MULSS xmm1,xmm2/m32 A V/V SSE Multiply the low single precision floating-point value in xmm2/m32 by the low single precision floating-point value in xmm1.
VEX.LIG.F3.0F.WIG 59 /r VMULSS xmm1,xmm2, xmm3/m32 B V/V AVX Multiply the low single precision floating-point value in xmm3/m32 by the low single precision floating-point value in xmm2.
EVEX.LLIG.F3.0F.W0 59 /r VMULSS xmm1 {k1}{z}, xmm2, xmm3/m32 {er} C V/V AVX512F OR AVX10.1 Multiply the low single precision floating-point value in xmm3/m32 by the low single precision floating-point value in xmm2.

Instruction Operand Encoding

Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
A N/A ModRM:reg (r, w) ModRM:r/m (r) N/A N/A
B N/A ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
C Tuple1 Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A

Description

Multiplies the low single precision floating-point value from the second source operand by the low single precision floating-point value in the first source operand, and stores the single precision floating-point result in the destination operand. The second source operand can be an XMM register or a 32-bit memory location. The first source operand and the destination operands are XMM registers. 128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAXVL1:32) of the corresponding YMM destination register remain unchanged. VEX.128 and EVEX encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The three high-order doublewords of the destination operand are copied from the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed. EVEX encoded version: The low doubleword element of the destination operand is updated according to the writemask. Software should ensure VMULSS is encoded with VEX.L=0. Encoding VMULSS with VEX.L=1 may encounter unpredictable behavior across different processor generations. MULSS—Multiply Scalar Single Precision Floating-Point Values Vol. 2B 4-151

Operation

VMULSS (EVEX Encoded Version)
IF (EVEX.b = 1) AND SRC2 *is a register*
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
IF k1[0] or *no writemask*
THEN   DEST[31:0] := SRC1[31:0] * SRC2[31:0]
ELSE
IF *merging-masking*                                 ; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE                                                         ; zeroing-masking
THEN DEST[31:0] := 0
FI
FI;
ENDFOR
DEST[127:32] := SRC1[127:32]
DEST[MAXVL-1:128] := 0

VMULSS (VEX.128 Encoded Version)
DEST[31:0] := SRC1[31:0] * SRC2[31:0]
DEST[127:32] := SRC1[127:32]
DEST[MAXVL-1:128] := 0

MULSS (128-bit Legacy SSE Version)
DEST[31:0] := DEST[31:0] * SRC[31:0]
DEST[MAXVL-1:32] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VMULSS __m128 _mm_mask_mul_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);
VMULSS __m128 _mm_maskz_mul_ss( __mmask8 k, __m128 a, __m128 b);
VMULSS __m128 _mm_mul_round_ss( __m128 a, __m128 b, int);
VMULSS __m128 _mm_mask_mul_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VMULSS __m128 _mm_maskz_mul_round_ss( __mmask8 k, __m128 a, __m128 b, int);
MULSS __m128 _mm_mul_ss(__m128 a, __m128 b)

Exceptions

SIMD Floating-Point Exceptions

Underflow, Overflow, Invalid, Precision, Denormal.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-20, “Type 3 Class Exception Conditions.” EVEX-encoded instruction, see Table 2-49, “Type E3 Class Exception Conditions.” MULSS—Multiply Scalar Single Precision Floating-Point Values Vol. 2B 4-152