kaddb

Add Masks Byte

KADDB k1, k2, k3

Adds two 8-bit mask registers.

Pseudocode Operation

k1 ← (k2 + k3)[7:0]

Encoding

Binary Layout

EVEX

Format EVEX

Opcode VEX.L1.66.0F.W0 4A /r

Extension AVX-512DQ

Operands

dest
k-reg
src1
k-reg
src2
k-reg

Reference

View in Intel® 64 and IA-32 Architectures SDM ↗ Intel® SDM

Instruction Forms

Opcode	Instruction	64/32-bit Mode	CPUID	Description
VEX.L1.0F.W0 4A /r	KADDW k1, k2, k3	V/V	RVR AVX512DQ OR AVX10.1	Add 16 bits masks in k2 and k3 and place result in k1.
VEX.L1.66.0F.W0 4A /r	KADDB k1, k2, k3	V/V	RVR AVX512DQ OR AVX10.1	Add 8 bits masks in k2 and k3 and place result in k1.
VEX.L1.0F.W1 4A /r	KADDQ k1, k2, k3	V/V	RVR AVX512BW OR AVX10.1	Add 64 bits masks in k2 and k3 and place result in k1.
VEX.L1.66.0F.W1 4A /r	KADDD k1, k2, k3	V/V	RVR AVX512BW OR AVX10.1	Add 32 bits masks in k2 and k3 and place result in k1.

Description

Adds the vector mask k2 and the vector mask k3, and writes the result into vector mask k1.

Operation

KADDW
DEST[15:0] := SRC1[15:0] + SRC2[15:0]
DEST[MAX_KL-1:16] := 0

KADDB
DEST[7:0] := SRC1[7:0] + SRC2[7:0]
DEST[MAX_KL-1:8] := 0

KADDQ
DEST[63:0] := SRC1[63:0] + SRC2[63:0]
DEST[MAX_KL-1:64] := 0

KADDD
DEST[31:0] := SRC1[31:0] + SRC2[31:0]
DEST[MAX_KL-1:32] := 0

Intel C/C++ Compiler Intrinsic Equivalent

KADDW __mmask16 _kadd_mask16 (__mmask16 a, __mmask16 b);
KADDB __mmask8 _kadd_mask8 (__mmask8 a, __mmask8 b);
KADDQ __mmask64 _kadd_mask64 (__mmask64 a, __mmask64 b);
KADDD __mmask32 _kadd_mask32 (__mmask32 a, __mmask32 b);

Flags Affected

None.

Exceptions

SIMD Floating-Point Exceptions

None. KADDW/KADDB/KADDQ/KADDD-ADD Two Masks Vol. 2A 3-513

Other Exceptions

See Table 2-65, “TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg).” KADDW/KADDB/KADDQ/KADDD-ADD Two Masks Vol. 2A 3-514