vcvtne2ps2bf16
Convert Two Packed Single to Packed BFloat16
VCVTNE2PS2BF16 zmm1 {k1}, zmm2, zmm3/m512
Converts two float vectors to one BFloat16 vector.
Details
Converts two packed single-precision (FP32) vectors into one packed bfloat16 vector by interleaving and rounding, producing 32 bfloat16 values in the destination ZMM register. The 'ne2' notation indicates two inputs are consumed to produce one output with truncation-based rounding (not MXCSR-controlled). Requires AVX-512-BF16; results are written under EVEX mask control; no arithmetic flags are modified.
Pseudocode Operation
for i = 0 to 15:
if (k1[2*i] == 1 or k1[2*i+1] == 1):
fp32_val1 ← zmm2[32*i:32*i+31]
fp32_val2 ← zmm3/m512[32*i:32*i+31]
zmm1[16*(2*i):16*(2*i)+15] ← convert_to_bf16_truncate(fp32_val1)
zmm1[16*(2*i+1):16*(2*i+1)+15] ← convert_to_bf16_truncate(fp32_val2)
else if (EVEX.z == 1):
zmm1[16*(2*i):16*(2*i)+31] ← 0
// else zmm1 unchanged
Example
VCVTNE2PS2BF16 zmm1, zmm2, zmm3/m512
Encoding
Binary Layout
EVEX
+0
72
+4
Operands
-
dest
512-bit ZMM AVX-512 register -
src1
512-bit ZMM AVX-512 register -
src2
512-bit ZMM AVX-512 register or Memory operand
Reference (Intel® SDM)
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| EVEX.128.F2.0F38.W0 72 /r | VCVTNE2PS2BF16 xmm1{k1}{z}, xmm2, xmm3/m128/m32bcst | A | V/V | (AVX512_BF16 AND AVX512VL) OR AVX10.1 | Convert packed single data from xmm2 and xmm3/m128/m32bcst to packed BF16 data in xmm1 with writemask k1. |
| EVEX.256.F2.0F38.W0 72 /r | VCVTNE2PS2BF16 ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst | A | V/V | (AVX512_BF16 AND AVX512VL) OR AVX10.1 | Convert packed single data from ymm2 and ymm3/m256/m32bcst to packed BF16 data in ymm1 with writemask k1. |
| EVEX.512.F2.0F38.W0 72 /r | VCVTNE2PS2BF16 zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst | A | V/V | (AVX512_BF16 AND AVX512F) OR AVX10.1 | Convert packed single data from zmm2 and zmm3/m512/m32bcst to packed BF16 data in zmm1 with writemask k1. |
Instruction Operand Encoding
| Op/En | Tuple Type | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|---|
| A | Full | ModRM:reg (w) | EVEX.vvvv (r) | ModRM:r/m (r) | N/A |
Description
Converts two SIMD registers of packed single data into a single register of packed BF16 data.
This instruction does not support memory fault suppression.
This instruction uses “Round to nearest (even)” rounding mode. Output denormals are always flushed to zero and input denormals are always treated as zero. MXCSR is not consulted nor updated. No floating-point exceptions are generated.
Operation
VCVTNE2PS2BF16 dest, src1, src2 VL = (128, 256, 512) KL = VL/16 origdest := dest FOR i := 0 to KL-1: IF k1[ i ] or *no writemask*: IF i < KL/2: IF src2 is memory and evex.b == 1: t := src2.fp32[0] ELSE: t := src2.fp32[ i ] ELSE: t := src1.fp32[ i-KL/2] // See VCVTNEPS2BF16 for definition of convert helper function dest.word[i] := convert_fp32_to_bfloat16(t) ELSE IF *zeroing*: dest.word[ i ] := 0 ELSE: // Merge masking, dest element unchanged dest.word[ i ] := origdest.word[ i ] DEST[MAXVL-1:VL] := 0 VCVTNE2PS2BF16—Convert Two Packed Single Data to One Packed BF16 Data Vol. 2C 5-32
Intel C/C++ Compiler Intrinsic Equivalent
VCVTNE2PS2BF16 __m128bh _mm_cvtne2ps_pbh (__m128, __m128); VCVTNE2PS2BF16 __m128bh _mm_mask_cvtne2ps_pbh (__m128bh, __mmask8, __m128, __m128); VCVTNE2PS2BF16 __m128bh _mm_maskz_cvtne2ps_pbh (__mmask8, __m128, __m128); VCVTNE2PS2BF16 __m256bh _mm256_cvtne2ps_pbh (__m256, __m256); VCVTNE2PS2BF16 __m256bh _mm256_mask_cvtne2ps_pbh (__m256bh, __mmask16, __m256, __m256); VCVTNE2PS2BF16 __m256bh _mm256_maskz_cvtne2ps_ pbh (__mmask16, __m256, __m256); VCVTNE2PS2BF16 __m512bh _mm512_cvtne2ps_pbh (__m512, __m512); VCVTNE2PS2BF16 __m512bh _mm512_mask_cvtne2ps_pbh (__m512bh, __mmask32, __m512, __m512); VCVTNE2PS2BF16 __m512bh _mm512_maskz_cvtne2ps_pbh (__mmask32, __m512, __m512);
Exceptions
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-52, “Type E4NF Class Exception Conditions.”
VCVTNE2PS2BF16—Convert Two Packed Single Data to One Packed BF16 Data Vol. 2C 5-33