pfsub

Packed Floating-Point Subtract

PFSUB mm, mm/m64

Subtracts packed floats (3DNow!).

Pseudocode Operation

dest[31:0] ← float_sub(dest[31:0], src[31:0]); dest[63:32] ← float_sub(dest[63:32], src[63:32]);

Encoding

Binary Layout

0F

+0

0F

+1

ModRM

+2

9A

+3

 

Format 3DNow!

Opcode 0F 0F /r 9A

Extension 3DNow!

Operands

• dest
  64-bit MMX register
• src
  64-bit MMX register or Memory operand

Related

More in 3DNow!

Reference

View in Intel® 64 and IA-32 Architectures SDM ↗ AMD APM

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
0F 0F /r 9A	PFSUB mmx1, mmx2/m64				Subtracts each packed single-precision floating-point value in the second source operand from the corresponding value in the first source operand.

Description

Subtracts packed single-precision floating-point values in an MMX register or 64-bit memory location from another MMX register (3DNow!).