neg
Two's Complement Negation
NEG r/m
Negates value (0 - operand).
Details
Performs two's complement negation (0 - operand), storing the result back in the operand. Sets/clears CF, OF, ZF, SF, AF, PF based on result; CF is set unless operand was zero. Available in 8/16/32/64-bit variants.
Pseudocode Operation
old_operand ← dest;
result ← 0 - dest;
dest ← result;
CF ← (old_operand != 0);
OF ← (old_operand == (1 << (operand_size * 8 - 1)));
ZF ← (result == 0);
SF ← (result & sign_bit) != 0;
PF ← popcount(result & 0xFF) % 2 == 0;
AF ← ((0 - old_operand) & 0x10) != (old_operand & 0x10);Example
NEG rbx
Encoding
Binary Layout
F7
+0
ModRM
+1
Operands
-
dest
Register or memory operand
Reference (Intel® SDM)
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| F6 /3 | NEG r/m8 | M | Valid Valid | Two's complement negate r/m8. | |
| F7 /3 | NEG r/m16 | M | Valid Valid | Two's complement negate r/m16. | |
| F7 /3 | NEG r/m32 | M | Valid Valid | Two's complement negate r/m32. | |
| REX.W + F7 /3 | NEG r/m64 | M | Valid N.E. | Two's complement negate r/m64. |
Description
Replaces the value of operand (the destination operand) with its two's complement. (This operation is equivalent to subtracting the operand from 0.) The destination operand is located in a general-purpose register or a memory location.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.
Operation
IF DEST = 0 THEN CF := 0; ELSE CF := 1; FI; DEST := [– (DEST)]
Flags Affected
The CF flag set to 0 if the source operand is 0; otherwise it is set to 1. The OF, SF, ZF, AF, and PF flags are set according to the result.
Exceptions
Protected Mode Exceptions
#GP(0) If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD If the LOCK prefix is used but the destination is not a memory operand.
Real-Address Mode Exceptions
#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
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#SS If a memory operand effective address is outside the SS segment limit.
#UD If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made.
#UD If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same as for protected mode exceptions.
64-Bit Mode Exceptions
#SS(0) If a memory address referencing the SS segment is in a non-canonical form.
#GP(0) If the memory address is in a non-canonical form.
#PF(fault-code) For a page fault.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD If the LOCK prefix is used but the destination is not a memory operand.
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