tileloaddt1

Load Tile Data (T1 Hint)

TILELOADDT1 tmm1, m

Loads data into an AMX tile register with T1 hint.

Details

Loads tile data from memory into an AMX tile register with a T1 (temporal) cache hint, indicating the data is likely to be used soon. The memory operand is typically addressed via a base register and optional displacement, and the tile dimensions are pre-configured via TILECONFIG. No flags are affected.

Pseudocode Operation

tmm1 = load_from_memory_with_t1_hint(m);
// Tile shape determined by previously configured palette and TILECFG register

Example

TILELOADDT1 tmm1, [rbp-8]

Encoding

Binary Layout

VEX

opcode

ModRM

Format VEX

Opcode VEX.128.66.0F38.W0 4B !(11):rrr:100

Extension AMX-TILE

Operands

dest
AMX tile register
src
Memory operand

Reference (Intel® SDM)

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
VEX.128.F2.0F38.W0 4B !(11):rrr:100	TILELOADD tmm1, sibmem	A	V/N.E.	AMX_TILE	Load data into tmm1 as specified by information in sibmem.
VEX.128.66.0F38.W0 4B !(11):rrr:100	TILELOADDT1 tmm1, sibmem	A	V/N.E.	AMX_TILE	Load data into tmm1 as specified by information in sibmem with hint to optimize data caching.

Instruction Operand Encoding

Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
A	N/A	ModRM:reg (w)	ModRM:r/m (r)	N/A	N/A

Description

This instruction is required to use SIB addressing. The index register serves as a stride indicator. If the SIB encoding omits an index register, the value zero is assumed for the content of the index register. This instruction loads a tile destination with rows and columns as specified by the tile configuration. The “T1” version provides a hint to the implementation that the data would be reused but does not need to be resident in the nearest cache levels. The TILECFG.start_row in the TILECFG data should be initialized to '0' in order to load the entire tile and is set to zero on successful completion of the TILELOADD instruction. TILELOADD is a restartable instruction and the TILECFG.start_row will be non-zero when restartable events occur during the instruction execution. Only memory operands are supported and they can only be accessed using a SIB addressing mode, similar to the V[P]GATHER*/V[P]SCATTER* instructions. Any attempt to execute the TILELOADD/TILELOADDT1 instructions inside an Intel TSX transaction will result in a transaction abort.

Operation

TILELOADD[,T1] tdest, tsib

start := tilecfg.start_row

zero_upper_rows(tdest,start)

membegin := tsib.base + displacement
// if no index register in the SIB encoding, the value zero is used.
stride := tsib.index << tsib.scale
nbytes := tdest.colsb
while start < tdest.rows:
memptr := membegin + start * stride
write_row_and_zero(tdest, start, read_memory(memptr, nbytes), nbytes)
start := start + 1
zero_tilecfg_start()
// In the case of a memory fault in the middle of an instruction, the tilecfg.start_row := start

Intel C/C++ Compiler Intrinsic Equivalent

TILELOADD void _tile_loadd(__tile dst, const void *base, int stride);
TILELOADDT1 void _tile_stream_loadd(__tile dst, const void *base, int stride);
TILELOADD/TILELOADDT1—Load Tile                                                                                                            Vol. 2B 4-723

Flags Affected

None. Exceptions AMX-E3; see Section 2.10, “Intel® AMX Instruction Exception Classes,” for details. TILELOADD/TILELOADDT1—Load Tile Vol. 2B 4-724