tilezero

Zero Tile

TILEZERO tmm1

Clears an AMX tile register.

Details

Clears all elements of an AMX tile register to zero. The tile retains its configured dimensions; only the data elements are zeroed. This instruction is a common initialization step for accumulator tiles before performing matrix operations. Requires AMX-TILE extension and valid tile configuration. No flags are affected.

Pseudocode Operation

rows ← tilecfg_state.rows[tmm1]; cols ← tilecfg_state.cols[tmm1]; for (i = 0; i < rows; i++) { for (j = 0; j < cols; j++) { tmm1[i, j] ← 0; } }

Example

TILEZERO tmm1

Encoding

Binary Layout
VEX
+0
opcode
+3
ModRM
+4
 
Format VEX
Opcode VEX.128.F2.0F38.W0 49 11:rrr:000
Extension AMX-TILE

Operands

  • dest
    AMX tile register

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
VEX.128.F2.0F38.W0 49 11:rrr:000 TILEZERO tmm1 A V/N.E. AMX_TILE Zero the destination tile.

Instruction Operand Encoding

Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
A N/A ModRM:reg (w) N/A N/A N/A

Description

This instruction zeroes the destination tile. Any attempt to execute the TILEZERO instruction inside an Intel TSX transaction will result in a transaction abort.

Operation

TILEZERO tdest

nbytes := palette_table[palette_id].bytes_per_row

for i in 0 ... palette_table[palette_id].max_rows-1:
for j in 0 ... nbytes-1:
tdest.row[i].byte[j] := 0
zero_tilecfg_start()

Intel C/C++ Compiler Intrinsic Equivalent

TILEZERO void _tile_zero(__tile dst);

Flags Affected

None. Exceptions AMX-E5; see Section 2.10, “Intel® AMX Instruction Exception Classes,” for details. TILEZERO—Zero Tile Vol. 2B 4-727