vperm2f128

Permute Floating-Point 128-bit Blocks

VPERM2F128 ymm1, ymm2, ymm3/m256, imm8

Shuffles 128-bit float lanes between YMM registers.

Details

Rearranges two 128-bit blocks from two 256-bit YMM operands into the destination 256-bit YMM register according to an 8-bit immediate selector. Bits [3:0] select which 128-bit half goes to the low 128 bits, bits [7:4] select the high 128 bits; bit 3 can zero-out the selected half. No flags are modified.

Pseudocode Operation

imm8 ← src3; x ← imm8[3:0]; y ← imm8[7:4]; if (imm8[3]) { dest[127:0] ← 0; } else { dest[127:0] ← (x[2:0]==0) ? src1[127:0] : (x[2:0]==1) ? src1[255:128] : (x[2:0]==2) ? src2[127:0] : src2[255:128]; } if (imm8[7]) { dest[255:128] ← 0; } else { dest[255:128] ← (y[2:0]==0) ? src1[127:0] : (y[2:0]==1) ? src1[255:128] : (y[2:0]==2) ? src2[127:0] : src2[255:128]; }

Example

VPERM2F128 ymm1, ymm2, ymm3/m256, 3

Encoding

Binary Layout

VEX

Format VEX

Opcode VEX.256.66.0F3A.W0 06 /r ib

Extension AVX

Operands

dest
256-bit YMM AVX register
src1
256-bit YMM AVX register
src2
256-bit YMM AVX register or Memory operand
src3
8-bit signed immediate

Reference (Intel® SDM)

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
VEX.256.66.0F3A.W0 06 /r ib	VPERM2F128 ymm1, ymm2, ymm3/m256, imm8	RV	V/V	AVX MI	Permute 128-bit floating-point fields in ymm2 and ymm3/mem using controls from imm8 and store result in ymm1.

Description

Permute 128 bit floating-point-containing fields from the first source operand (second operand) and second source operand (third operand) using bits in the 8-bit immediate and store results in the destination operand (first operand). The first source operand is a YMM register, the second source operand is a YMM register or a 256-bit memory location, and the destination operand is a YMM register. SRC2 Y1 Y0 SRC1 X1 X0 DEST X0, X1, Y0, or Y1 X0, X1, Y0, or Y1 Figure 5-21. VPERM2F128 Operation Imm8[1:0] select the source for the first destination 128-bit field, imm8[5:4] select the source for the second destination field. If imm8[3] is set, the low 128-bit field is zeroed. If imm8[7] is set, the high 128-bit field is zeroed. VEX.L must be 1, otherwise the instruction will #UD. VPERM2F128—Permute Floating-Point Values Vol. 2C 5-494

Operation

VPERM2F128
CASE IMM8[1:0] of
0: DEST[127:0] := SRC1[127:0]
1: DEST[127:0] := SRC1[255:128]
2: DEST[127:0] := SRC2[127:0]
3: DEST[127:0] := SRC2[255:128]
ESAC

CASE IMM8[5:4] of
0: DEST[255:128] := SRC1[127:0]
1: DEST[255:128] := SRC1[255:128]
2: DEST[255:128] := SRC2[127:0]
3: DEST[255:128] := SRC2[255:128]
ESAC
IF (imm8[3])
DEST[127:0] := 0
FI

IF (imm8[7])
DEST[MAXVL-1:128] := 0
FI

Intel C/C++ Compiler Intrinsic Equivalent

VPERM2F128:   __m256 _mm256_permute2f128_ps (__m256 a, __m256 b, int control)
VPERM2F128:   __m256d _mm256_permute2f128_pd (__m256d a, __m256d b, int control)
VPERM2F128:   __m256i _mm256_permute2f128_si256 (__m256i a, __m256i b, int control)

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-23, “Type 6 Class Exception Conditions.” Additionally: #UD If VEX.L = 0 If VEX.W = 1. VPERM2F128—Permute Floating-Point Values Vol. 2C 5-495