sha256msg1

SHA256 Message Schedule 1

SHA256MSG1 xmm1, xmm2/m128

Performs intermediate calculation for SHA256 message schedule.

Details

Performs the first intermediate step of SHA-256 message schedule expansion on 128-bit XMM operands, computing partial W values for the message schedule. The destination is updated with results of the partial expansion; no flags are affected.

Pseudocode Operation

W[0..3] ← dest[0..3];
W[4..7] ← src[0..3];
for i in 0..3:
  dest[i] ← W[i] + SHA256_GAMMA0(W[i+1]);

Example

SHA256MSG1 xmm1, xmm2/m128

Encoding

Binary Layout
0F
+0
38
+1
CC
+2
 
Format Legacy
Opcode NP 0F 38 CC /r
Extension SHA

Operands

  • dest
    128-bit XMM SIMD register
  • src
    128-bit XMM SIMD register or Memory operand

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
NP 0F 38 CC /r SHA256MSG1 xmm1, xmm2/m128 RM V/V SHA Performs an intermediate calculation for the next four SHA256 message dwords using previous message dwords from xmm1 and xmm2/m128, storing the result in xmm1.

Description

The SHA256MSG1 instruction is one of two SHA256 message scheduling instructions. The instruction performs an intermediate calculation for the next four SHA256 message dwords.

Operation

SHA256MSG1
W4 := SRC2[31: 0] ;
W3 := SRC1[127:96] ;
W2 := SRC1[95:64] ;
W1 := SRC1[63: 32] ;
W0 := SRC1[31: 0] ;

DEST[127:96] := W3 + σ0( W4);
DEST[95:64] := W2 + σ0( W3);
DEST[63:32] := W1 + σ0( W2);
DEST[31:0] := W0 + σ0( W1);

Intel C/C++ Compiler Intrinsic Equivalent

SHA256MSG1 __m128i _mm_sha256msg1_epu32(__m128i, __m128i);

Flags Affected

None.

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-21, “Type 4 Class Exception Conditions.” SHA256MSG1—Perform an Intermediate Calculation for the Next Four SHA256 Message Dwords Vol. 2B 4-635