vmxoff
Leave VMX Operation
Leaves VMX root operation.
Details
Exits VMX root operation and returns the processor to non-VMX mode. This instruction requires VMX root operation and clears the VMXE bit in CR4. CF and ZF flags are set to indicate error conditions if the operation fails; execution may be serialized.
Pseudocode Operation
if (VMX_root_operation) {
VMX_mode ← OFF;
CR4.VMXE ← 0;
CF ← 0;
ZF ← 0;
} else {
CF ← 1;
ZF ← 1;
}
Example
Encoding
Operands
Reference (Intel® SDM)
Instruction Forms
| Opcode | Instruction | Op/En | 64/32-bit Mode | CPUID | Description |
|---|---|---|---|---|---|
| 0F 01 C4 | VMXOFF | ZO | Leaves VMX operation. |
Description
Operation
IF (not in VMX operation) or (CR0.PE = 0) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0) THEN #UD; ELSIF in VMX non-root operation THEN VMexit; ELSIF CPL > 0 or in SEAM root operation THEN #GP(0); ELSIF dual-monitor treatment of SMIs and SMM is active THEN VMfail(VMXOFF under dual-monitor treatment of SMIs and SMM); ELSE leave VMX operation; unblock INIT; IF IA32_SMM_MONITOR_CTL[2] = 02 THEN unblock SMIs; IF outside SMX operation3 THEN unblock and enable A20M; FI; IF the processor supports SEAM THEN ensure that data for each active SEAM VMCS is in the memory of the corresponding VMCS region; FI; clear address-range monitoring; VMsucceed; FI;
Flags Affected
See the operation section and Section 33.2. 1. See the information on MONITOR/MWAIT in Chapter 11, “Multiple-Processor Management,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A. 2. Setting IA32_SMM_MONITOR_CTL[bit 2] to 1 prevents VMXOFF from unblocking SMIs regardless of the value of the register’s value bit (bit 0). Not all processors allow this bit to be set to 1. Software should consult the VMX capability MSR IA32_VMX_MISC (see Appendix A.6) to determine whether this is allowed. 3. A logical processor is outside SMX operation if GETSEC[SENTER] has not been executed or if GETSEC[SEXIT] was executed after the last execution of GETSEC[SENTER]. See Chapter 6, “Safer Mode Extensions Reference.”