kshiftrd

Shift Right Mask Doubleword

KSHIFTRD k1, k2, imm8

Logically shifts 32-bit mask right.

Pseudocode Operation

dest ← (src1 >> imm8) & 0xFFFFFFFF;

Example

KSHIFTRD k1, k2, 3

Encoding

Binary Layout

EVEX

Format EVEX

Opcode VEX.L0.66.0F3A.W0 31 /r

Extension AVX-512BW

Operands

dest
AVX-512 opmask register (k0-k7)
src1
AVX-512 opmask register (k0-k7)
src2
8-bit signed immediate

Reference

View in Intel® 64 and IA-32 Architectures SDM ↗ Intel® SDM

Instruction Forms

Opcode	Instruction	64/32-bit Mode	CPUID	Description
VEX.L0.66.0F3A.W1 30 /r	KSHIFTRW k1, k2, imm8	V/V	RRI AVX512F OR AVX10.1	Shift right 16 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W0 30 /r	KSHIFTRB k1, k2, imm8	V/V	RRI AVX512DQ OR AVX10.1	Shift right 8 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W1 31 /r	KSHIFTRQ k1, k2, imm8	V/V	RRI AVX512BW OR AVX10.1	Shift right 64 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W0 31 /r	KSHIFTRD k1, k2, imm8	V/V	RRI AVX512BW OR AVX10.1	Shift right 32 bits in k2 by immediate and write result in k1.

Description

Shifts 8/16/32/64 bits in the second operand (source operand) right by the count specified in immediate and place the least significant 8/16/32/64 bits of the result in the destination operand. The higher bits of the destination are zero-extended. The destination is set to zero if the count value is greater than 7 (for byte shift), 15 (for word shift), 31 (for doubleword shift) or 63 (for quadword shift).

Operation

KSHIFTRW
COUNT := imm8[7:0]
DEST[MAX_KL-1:0] := 0
IF COUNT <=15
THEN DEST[15:0] := SRC1[15:0] >> COUNT;
FI;

KSHIFTRB
COUNT := imm8[7:0]
DEST[MAX_KL-1:0] := 0
IF COUNT <=7
THEN   DEST[7:0] := SRC1[7:0] >> COUNT;
FI;

KSHIFTRQ
COUNT := imm8[7:0]
DEST[MAX_KL-1:0] := 0
IF COUNT <=63
THEN   DEST[63:0] := SRC1[63:0] >> COUNT;
FI;

KSHIFTRD
COUNT := imm8[7:0]
DEST[MAX_KL-1:0] := 0
IF COUNT <=31
THEN   DEST[31:0] := SRC1[31:0] >> COUNT;
FI;

Intel C/C++ Compiler Intrinsic Equivalent

Compiler auto generates KSHIFTRW when needed.

Flags Affected

None.

Exceptions

SIMD Floating-Point Exceptions