Add With Carry
Add two operands plus an incoming carry bit, for multi-word arithmetic.
Arithmetic
Semantics
rd = rs1 + rs2 + carry_in, with carry_out produced for the next word. This is the clearest place the flag-register architectures diverge from RISC-V, which has no architectural carry flag at all.
| Architecture | Instructions | Expressed as | How this architecture does it |
|---|---|---|---|
| x86 | one instruction | ADC adds the CF flag set by a previous ADD, the standard multi-precision idiom. | |
| ARM | one instruction | ADC uses the C flag from PSTATE; ADCS both uses and updates it for chained words. | |
| RISC-V | none | not available | RISC-V has no architectural carry flag, a deliberate design decision to keep instructions independent and simplify out-of-order renaming. Multi-word addition is done with an explicit comparison: add the words, then SLTU the sum against an operand to materialize the carry into a register. |
| PowerISA | one instruction | addc generates the carry into the XER CA bit; adde consumes it, so a multi-word chain is addc followed by a run of adde. |
Other operations
Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Enable and Disable Interrupts Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Instruction Cache Synchronisation Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load and Store Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Materialise a Large Constant Memory Barrier / Fence Multiply High No Operation PC-Relative Address Population Count Read Cycle Counter Return From Exception Rotate Left Sign Extend Byte Speculation Barrier Spin-Wait Hint Stack Push and Pop System Call