Add With Carry
Add two operands plus an incoming carry bit, for multi-word arithmetic.
Arithmetic
Semantics
rd = rs1 + rs2 + carry_in, with carry_out produced for the next word. This is the clearest place the flag-register architectures diverge from RISC-V, which has no architectural carry flag at all.
| Architecture | Instructions | Expressed as | How this architecture does it |
|---|---|---|---|
| x86 | one instruction | ADC adds the CF flag set by a previous ADD, the standard multi-precision idiom. | |
| ARM | one instruction | ADC uses the C flag from PSTATE; ADCS both uses and updates it for chained words. | |
| RISC-V | none | not available | RISC-V has no architectural carry flag, a deliberate design decision to keep instructions independent and simplify out-of-order renaming. Multi-word addition is done with an explicit comparison: add the words, then SLTU the sum against an operand to materialize the carry into a register. |
| PowerISA | one instruction | addc generates the carry into the XER CA bit; adde consumes it, so a multi-word chain is addc followed by a run of adde. |
Other operations
Atomic Compare and Swap Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Floating-Point Square Root Fused Multiply-Add Integer Addition Integer Divide Integer Multiply Load-Acquire Memory Barrier / Fence No Operation Population Count Rotate Left Sign Extend Byte System Call