Read Cycle Counter

Read a monotonically increasing hardware counter for timing.

System

Semantics

Every architecture provides one, but they differ in whether the counter measures core cycles or a fixed-rate clock, and in whether user code may read it without the OS enabling access.

Architecture Instructions Expressed as How this architecture does it
x86 one instruction Returns the time-stamp counter in EDX:EAX. On modern parts the TSC is invariant to frequency scaling and sleep states, which is what lets it be used as a clock rather than a cycle count. It can be restricted to privileged code by a control register bit.
ARM one instruction MRS reading CNTVCT_EL0 gives the virtual counter, a fixed-frequency system counter rather than core cycles, and is normally readable from user space. Actual cycle counts come from PMCCNTR_EL0, which the OS must enable first.
RISC-V one instruction Two counters kept deliberately separate: RDCYCLE counts core cycles and RDTIME a constant-rate wall clock, so code cannot silently confuse the two on a part that scales frequency. Both are CSR reads the OS may trap.
PowerISA one instruction MFTB reads the Time Base, a constant-rate counter readable from user mode. Cycle-accurate counts come from the performance monitor SPRs through MFSPR, which are privileged.

Other operations

Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Memory Barrier / Fence No Operation Population Count Rotate Left Sign Extend Byte Spin-Wait Hint System Call