Compare and Branch
Branch based on a comparison of two registers.
Control Flow
Semantics
if (rs1 <op> rs2) goto target. The deep split here is architectural: x86 and PowerISA compare into a flags/condition register and branch on it in a second instruction, while RISC-V fuses compare and branch into one instruction and AArch64 offers both styles.
| Architecture | Instructions | Expressed as | How this architecture does it |
|---|---|---|---|
| x86 | an idiom | Always two steps: CMP writes the flags, then a Jcc branches on them. Modern cores macro-fuse the pair into one operation. | |
| ARM | one instruction | Offers both styles: CBZ/CBNZ and TBZ/TBNZ fuse a comparison against zero (or a single bit test) with the branch, while CMP plus B.cond covers the general case. | |
| RISC-V | one instruction | There is no flags register: every conditional branch compares two registers directly, so BEQ/BNE/BLT/BGE are the whole mechanism. | |
| PowerISA | an idiom | Compare writes one of eight condition register fields, then bc branches on a selected bit, so independent comparisons can be kept live in different CR fields simultaneously. |
Other operations
Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Enable and Disable Interrupts Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Instruction Cache Synchronisation Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load and Store Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Materialise a Large Constant Memory Barrier / Fence Multiply High No Operation PC-Relative Address Population Count Read Cycle Counter Return From Exception Rotate Left Sign Extend Byte Speculation Barrier Spin-Wait Hint Stack Push and Pop System Call