RV32I Instructions
38 RISC-V instructions in this extension - click any row for encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Summary |
|---|---|---|---|
| ADD | ADD rd, rs1, rs2 | R-Type | Adds the contents of two registers. |
| ADDI | ADDI rd, rs1, imm | I-Type | Adds a register and a sign-extended 12-bit immediate value. |
| AND | AND rd, rs1, rs2 | R-Type | Performs a bitwise logical AND operation between two registers. |
| ANDI | ANDI rd, rs1, imm | I-Type | Performs a bitwise logical AND between a register and a sign-extended 12-bit immediate. |
| AUIPC | AUIPC rd, imm | U-Type | Adds a 20-bit upper immediate to the Program Counter, used for PC-relative addressing. |
| BEQ | BEQ rs1, rs2, offset | B-Type | Take the branch if registers rs1 and rs2 are equal. |
| BGE | BGE rs1, rs2, offset | B-Type | Take the branch if rs1 is greater than or equal to rs2 (signed). |
| BGEU | BGEU rs1, rs2, offset | B-Type | Take the branch if rs1 is greater than or equal to rs2 (unsigned comparison). |
| BLT | BLT rs1, rs2, offset | B-Type | Take the branch if rs1 is less than rs2 (signed). |
| BLTU | BLTU rs1, rs2, offset | B-Type | Take the branch if rs1 is less than rs2 (unsigned comparison). |
| BNE | BNE rs1, rs2, offset | B-Type | Take the branch if registers rs1 and rs2 are not equal. |
| EBREAK | EBREAK | I-Type | Used by debuggers to cause control to be transferred back to a debugging environment. |
| ECALL | ECALL | I-Type | Generates an environment call exception (system call). |
| FENCE | FENCE pred, succ | I-Type | Orders device I/O and memory accesses. |
| JAL | JAL rd, offset | J-Type | Jumps to an offset relative to PC and saves the return address (PC+4) to rd. |
| JALR | JALR rd, offset(rs1) | I-Type | Jumps to address in rs1 + offset, saving return address to rd. |
| LB | LB rd, offset(rs1) | I-Type | Loads an 8-bit byte from memory and sign-extends it to the register width. |
| LBU | LBU rd, offset(rs1) | I-Type | Loads an 8-bit byte from memory and zero-extends it. |
| LH | LH rd, offset(rs1) | I-Type | Loads a 16-bit halfword from memory and sign-extends it. |
| LHU | LHU rd, offset(rs1) | I-Type | Loads a 16-bit halfword from memory and zero-extends it. |
| LUI | LUI rd, imm | U-Type | Loads the 20-bit immediate into the upper 20 bits of the register (lower 12 bits are zero). |
| LW | LW rd, offset(rs1) | I-Type | Loads a 32-bit word from memory and sign-extends it to 64 bits. |
| OR | OR rd, rs1, rs2 | R-Type | Performs a bitwise logical OR operation. |
| ORI | ORI rd, rs1, imm | I-Type | Performs a bitwise logical OR with a sign-extended immediate. |
| SB | SB rs2, offset(rs1) | S-Type | Stores the lowest 8 bits of a register to memory. |
| SH | SH rs2, offset(rs1) | S-Type | Stores the lowest 16 bits of a register to memory. |
| SLL | SLL rd, rs1, rs2 | R-Type | Shifts a register left by the number of bits specified in another register. |
| SLLI | SLLI rd, rs1, shamt | I-Type (Shift) | Shifts a register left by a constant amount. |
| SLT | SLT rd, rs1, rs2 | R-Type | Sets rd to 1 if rs1 < rs2 (signed), otherwise 0. |
| SLTI | SLTI rd, rs1, imm | I-Type | Sets rd to 1 if rs1 < immediate (signed), otherwise 0. |
| SLTIU | SLTIU rd, rs1, imm | I-Type | Sets rd to 1 if rs1 < immediate (unsigned comparison), otherwise 0. |
| SLTU | SLTU rd, rs1, rs2 | R-Type | Sets rd to 1 if rs1 < rs2 (unsigned comparison), otherwise 0. |
| SRA | SRA rd, rs1, rs2 | R-Type | Shifts a register right, preserving the sign bit. |
| SRL | SRL rd, rs1, rs2 | R-Type | Shifts a register right, shifting in zeros. |
| SUB | SUB rd, rs1, rs2 | R-Type | Subtracts rs2 from rs1. |
| SW | SW rs2, offset(rs1) | S-Type | Stores a 32-bit word to memory. |
| XOR | XOR rd, rs1, rs2 | R-Type | Performs a bitwise logical Exclusive-OR operation. |
| XORI | XORI rd, rs1, imm | I-Type | Performs a bitwise logical Exclusive-OR with a sign-extended immediate. |