SRL

Shift Right Logical

SRL rd, rs1, rs2

Shifts a register right, shifting in zeros.

Encoding

Binary Layout

0000000

31:25

rs2

24:20

rs1

19:15

101

14:12

rd

11:7

0110011

6:0

 

Format R-Type

Opcode 0x00005033

Extension RV32I

Operands

• rd
  Destination register (integer)
• rs1
  Source
• rs2
  Shift Amount

Example

SRL x10, x11, x12

// Logical right shift.

Related

More in RV32I

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

SRL performs a logical right shift of the value in rs1 by the shift amount held in the lower 5 bits of rs2 (or 6 bits in RV64I), writing the result to rd. Zeros are shifted into the high-order bits.

Operation

R[rd] = R[rs1] >> (R[rs2] & 0x1F);