VOR.VI

Vector OR Immediate

VOR.VI vd, vs2, imm, vm

Bitwise OR with immediate.

Encoding

Binary Layout

001010

31:26

vm

25

vs2

24:20

simm5

19:15

011

14:12

vd

11:7

1010111

6:0

 

Format OPIVI

Opcode 0x28003057

Extension V

Operands

• vd
  Destination vector register
• vs2
  Source vector register 2
• imm
  Imm

Example

VOR.VI v1, v4, 16, v0.t

Related

More in V

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

Performs element-wise bitwise OR on a vector and an immediate, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.

Operation

vd = vs2 | imm;