VNMSUB.VV

Vector Integer Negative Multiply-Subtract

VNMSUB.VV vd, vs1, vs2, vm

Computes vd = -(vd - (vs1 * vs2)).

Encoding

Binary Layout

101011

31:26

vm

25

vs2

24:20

vs1

19:15

010

14:12

vd

11:7

1010111

6:0

 

Format OPIVV

Opcode 0xAC002057

Extension V

Operands

• vd
  Dest/Accumulator
• vs1
  Source vector register 1
• vs2
  Source vector register 2

Example

VNMSUB.VV v1, v2, v4, v0.t

Related

More in V

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

Performs a narrowing operation, halving the result element width relative to the source. Optionally saturates the result. Active elements are determined by vl; masking by vm.

Operation

foreach(i < vl): vd[i] = -(vd[i] - (vs1[i] * vs2[i]));