RISC-V Instructions
553 instructions — click any row to view encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Extension | Summary |
|---|---|---|---|---|
| ADD | ADD rd, rs1, rs2 | R-Type | RV32I | Adds the contents of two registers. |
| ADDI | ADDI rd, rs1, imm | I-Type | RV32I | Adds a register and a sign-extended 12-bit immediate value. |
| ADDIW | ADDIW rd, rs1, imm | I-Type | RV64I | Adds a 12-bit immediate to a register (32-bit arithmetic) and sign-extends to 64 bits. |
| ADDUW | ADDUW rd, rs1, rs2 | R-Type | Zba | Zero-extends the lower 32 bits of rs1 and adds it to rs2. Useful for 64-bit address calculations with 32-bit unsigned indices. |
| ADDW | ADDW rd, rs1, rs2 | R-Type | RV64I | Adds two 32-bit registers and sign-extends the result to 64 bits. |
| AES64DS | AES64DS rd, rs1, rs2 | R-Type | Zknd | Performs one round of AES-128 decryption key schedule generation. |
| AES64ES | AES64ES rd, rs1, rs2 | R-Type | Zkne | Performs one round of AES-128 encryption key schedule generation. |
| AES64IM | AES64IM rd, rs1 | R-Type | Zknd | Performs the Inverse MixColumns transformation for AES decryption (RV64). |
| AES64KS1I | AES64KS1I rd, rs1, rcon | I-Type | Zkne | Performs the first part of the AES-128/192/256 key schedule generation (RV64). |
| AES64KS2 | AES64KS2 rd, rs1, rs2 | R-Type | Zkne | Performs the second part of the AES-192/256 key schedule generation (RV64). |
| AMOADD.D | AMOADD.D rd, rs2, (rs1) | R-Type (Atomic) | A | Atomically adds a value to a 64-bit doubleword in memory. |
| AMOADD.W | AMOADD.W rd, rs2, (rs1) | R-Type (Atomic) | A | Atomically adds a value to a word in memory. |
| AMOAND.D | AMOAND.D rd, rs2, (rs1) | R-Type (Atomic) | A | Atomically performs bitwise AND on a 64-bit doubleword in memory. |
| AMOAND.W | AMOAND.W rd, rs2, (rs1) | R-Type (Atomic) | A | Atomically performs bitwise AND on a word in memory. |
| AMOCAS.D | AMOCAS.D rd, rs2, (rs1) | R-Type (Atomic) | Zacas | Atomically compares 64-bit memory at rs1 with rd; if equal, writes rs2 to memory. |
| AMOCAS.W | AMOCAS.W rd, rs2, (rs1) | R-Type (Atomic) | Zacas | Atomically compares memory at rs1 with rd; if equal, writes rs2 to memory. Returns original value in rd. |
| AMOMAX.D | AMOMAX.D rd, rs2, (rs1) | R-Type (Atomic) | A | Atomically updates memory with the maximum of the memory value and register value (64-bit Signed). |
| AMOMAX.W | AMOMAX.W rd, rs2, (rs1) | R-Type (Atomic) | A | Atomically updates memory with the maximum of the memory value and register value (Signed). |
| AMOMAXU.D | AMOMAXU.D rd, rs2, (rs1) | R-Type (Atomic) | A | Atomically updates memory with the maximum of the memory value and register value (Unsigned 64-bit). |
| AMOMAXU.W | AMOMAXU.W rd, rs2, (rs1) | R-Type (Atomic) | A | Atomically updates memory with the maximum of the memory value and register value (Unsigned). |
| AMOMIN.D | AMOMIN.D rd, rs2, (rs1) | R-Type (Atomic) | A | Atomically updates memory with the minimum of the memory value and register value (64-bit Signed). |
| AMOMIN.W | AMOMIN.W rd, rs2, (rs1) | R-Type (Atomic) | A | Atomically updates memory with the minimum of the memory value and register value (Signed). |
| AMOMINU.D | AMOMINU.D rd, rs2, (rs1) | R-Type (Atomic) | A | Atomically updates memory with the minimum of the memory value and register value (Unsigned 64-bit). |
| AMOMINU.W | AMOMINU.W rd, rs2, (rs1) | R-Type (Atomic) | A | Atomically updates memory with the minimum of the memory value and register value (Unsigned). |
| AMOOR.D | AMOOR.D rd, rs2, (rs1) | R-Type (Atomic) | A | Atomically performs bitwise OR on a 64-bit doubleword in memory. |
| AMOOR.W | AMOOR.W rd, rs2, (rs1) | R-Type (Atomic) | A | Atomically performs bitwise OR on a word in memory. |
| AMOSWAP.D | AMOSWAP.D rd, rs2, (rs1) | R-Type (Atomic) | A | Atomically swaps a 64-bit value in memory with a register. |
| AMOSWAP.W | AMOSWAP.W rd, rs2, (rs1) | R-Type (Atomic) | A | Atomically swaps a value in memory with a register. |
| AMOXOR.D | AMOXOR.D rd, rs2, (rs1) | R-Type (Atomic) | A | Atomically performs bitwise XOR on a 64-bit doubleword in memory. |
| AMOXOR.W | AMOXOR.W rd, rs2, (rs1) | R-Type (Atomic) | A | Atomically performs bitwise XOR on a word in memory. |
| AND | AND rd, rs1, rs2 | R-Type | RV32I | Performs a bitwise logical AND operation between two registers. |
| ANDI | ANDI rd, rs1, imm | I-Type | RV32I | Performs a bitwise logical AND between a register and a sign-extended 12-bit immediate. |
| ANDN | ANDN rd, rs1, rs2 | R-Type | Zbb | Performs bitwise AND with the bitwise negation of rs2 (rs1 & ~rs2). |
| AUIPC | AUIPC rd, imm | U-Type | RV32I | Adds a 20-bit upper immediate to the Program Counter, used for PC-relative addressing. |
| BCLR | BCLR rd, rs1, rs2 | R-Type | Zbs | Clears a single bit in rs1 at the index specified by rs2. |
| BCLRI | BCLRI rd, rs1, imm | I-Type | Zbs | Clears a single bit in rs1 at the index specified by an immediate. |
| BEQ | BEQ rs1, rs2, offset | B-Type | RV32I | Take the branch if registers rs1 and rs2 are equal. |
| BEQZ | BEQZ rs, offset | B-Type | Pseudo | Branches if the register is zero. |
| BEXT | BEXT rd, rs1, rs2 | R-Type | Zbs | Extracts the value of a single bit (0 or 1) at the index specified by rs2. The result is placed in the LSB of rd. |
| BEXTI | BEXTI rd, rs1, imm | I-Type | Zbs | Extracts the value of a single bit (0 or 1) at the index specified by an immediate. |
| BGE | BGE rs1, rs2, offset | B-Type | RV32I | Take the branch if rs1 is greater than or equal to rs2 (signed). |
| BGEU | BGEU rs1, rs2, offset | B-Type | RV32I | Take the branch if rs1 is greater than or equal to rs2 (unsigned comparison). |
| BINV | BINV rd, rs1, rs2 | R-Type | Zbs | Inverts (toggles) a single bit in rs1 at the index specified by rs2. |
| BINVI | BINVI rd, rs1, imm | I-Type | Zbs | Inverts (toggles) a single bit in rs1 at the index specified by an immediate. |
| BLT | BLT rs1, rs2, offset | B-Type | RV32I | Take the branch if rs1 is less than rs2 (signed). |
| BLTU | BLTU rs1, rs2, offset | B-Type | RV32I | Take the branch if rs1 is less than rs2 (unsigned comparison). |
| BNE | BNE rs1, rs2, offset | B-Type | RV32I | Take the branch if registers rs1 and rs2 are not equal. |
| BNEZ | BNEZ rs, offset | B-Type | Pseudo | Branches if the register is not zero. |
| BSET | BSET rd, rs1, rs2 | R-Type | Zbs | Sets a single bit in rs1 at the index specified by rs2. |
| BSETI | BSETI rd, rs1, imm | I-Type | Zbs | Sets a single bit in rs1 at the index specified by an immediate. |
| C.ADD | C.ADD rd, rs2 | CR | C | Adds two registers. |
| C.ADDI | C.ADDI rd, imm | CI | C | Adds a non-zero immediate to a register. |
| C.ADDI16SP | C.ADDI16SP imm | CI | C | Adds a signed non-zero immediate to the stack pointer (x2). |
| C.ADDI4SPN | C.ADDI4SPN rd', uimm | CIW | C | Adds a zero-extended non-zero immediate to the stack pointer (x2) and stores the result in a register. |
| C.ADDIW | C.ADDIW rd, imm | CI | C | Adds a signed immediate to a register (32-bit result sign-extended, RV64). |
| C.ADDW | C.ADDW rd', rs2' | CA | C | Adds two registers (32-bit result sign-extended, RV64). |
| C.AND | C.AND rd', rs2' | CA | C | Bitwise AND of two registers. |
| C.ANDI | C.ANDI rd', imm | CB | C | Computes bitwise AND with a signed immediate. |
| C.BEQZ | C.BEQZ rs1', offset | CB | C | Branches if the register is zero. |
| C.BNEZ | C.BNEZ rs1', offset | CB | C | Branches if the register is not zero. |
| C.EBREAK | C.EBREAK | CR | C | Triggers a debugger breakpoint. |
| C.FLD | C.FLD rd', offset(rs1') | CL | C | Loads a double-precision float from memory (Compressed). |
| C.FLDSP | C.FLDSP rd, offset(x2) | CI | C | Loads a double-precision float from the stack pointer. |
| C.FLW | C.FLW rd', offset(rs1') | CL | C | Loads a single-precision float from memory (Compressed). |
| C.FLWSP | C.FLWSP rd, offset(x2) | CI | C | Loads a single-precision float from the stack pointer. |
| C.FSD | C.FSD rs2', offset(rs1') | CS | C | Stores a double-precision float to memory (Compressed). |
| C.FSDSP | C.FSDSP rs2, offset(x2) | CSS | C | Stores a double-precision float to the stack pointer. |
| C.FSW | C.FSW rs2', offset(rs1') | CS | C | Stores a single-precision float to memory (Compressed). |
| C.FSWSP | C.FSWSP rs2, offset(x2) | CSS | C | Stores a single-precision float to the stack pointer. |
| C.J | C.J offset | CJ | C | Unconditional PC-relative jump. |
| C.JAL | C.JAL offset | CJ | C | Performs a PC-relative jump and stores return address in x1 (ra). RV32 only. |
| C.JALR | C.JALR rs1 | CR | C | Jumps to register address and links (saves PC+2 to ra). |
| C.JR | C.JR rs1 | CR | C | Unconditionally jumps to address in register. |
| C.LD | C.LD rd', offset(rs1') | CL | C | Loads a 64-bit value from memory (Compressed, RV64). |
| C.LDSP | C.LDSP rd, offset(x2) | CI | C | Loads a 64-bit value from the stack pointer (RV64). |
| C.LI | C.LI rd, imm | CI | C | Loads a 6-bit signed immediate into a register. |
| C.LUI | C.LUI rd, imm | CI | C | Loads a non-zero 6-bit immediate into bits 17-12 of the destination register, clears lower 12 bits, sign-extends bit 17. |
| C.LW | C.LW rd', offset(rs1') | CL | C | Loads a 32-bit word from memory using a compressed encoding. |
| C.LWSP | C.LWSP rd, offset(x2) | CI | C | Loads a word from the stack pointer (x2). |
| C.MUL | C.MUL rd', rs2' | CA | Zcb | Performs 32-bit multiplication (rd = rd * rs2) in 16-bit encoding. |
| C.MV | C.MV rd, rs2 | CR | C | Copies register rs2 to rd. |
| C.NOP | C.NOP | CI | C | Performs no operation (Compressed encoding). |
| C.NOT | C.NOT rd' | CR | Zcb | Computes bitwise logical negation. |
| C.OR | C.OR rd', rs2' | CA | C | Bitwise OR of two registers. |
| C.SD | C.SD rs2', offset(rs1') | CS | C | Stores a 64-bit value to memory (Compressed, RV64). |
| C.SDSP | C.SDSP rs2, offset(x2) | CSS | C | Stores a 64-bit value to the stack pointer (RV64). |
| C.SEXT.B | C.SEXT.B rd' | CR | Zcb | Sign extends the lowest byte of rd' to XLEN. |
| C.SLLI | C.SLLI rd, imm | CI | C | Logically shifts a register left by immediate. |
| C.SRAI | C.SRAI rd', imm | CB | C | Arithmetically shifts a register right by immediate. |
| C.SRLI | C.SRLI rd', imm | CB | C | Logically shifts a register right by immediate. |
| C.SUB | C.SUB rd', rs2' | CA | C | Subtracts two registers. |
| C.SUBW | C.SUBW rd', rs2' | CA | C | Subtracts two registers (32-bit result sign-extended, RV64). |
| C.SW | C.SW rs2', offset(rs1') | CS | C | Stores a 32-bit word to memory using a compressed encoding. |
| C.SWSP | C.SWSP rs2, offset(x2) | CSS | C | Stores a word to the stack pointer (x2). |
| C.XOR | C.XOR rd', rs2' | CA | C | Bitwise XOR of two registers. |
| C.ZEXT.B | C.ZEXT.B rd' | CR | Zcb | Zero extends the lowest byte of rd' to XLEN. |
| CALL | CALL symbol | Pseudo | Pseudo | Calls a function by jumping to an address and saving the return address. |
| CBO.CLEAN | CBO.CLEAN (rs1) | I-Type | Zicbom | Performs a clean operation on the cache block containing the effective address. |
| CBO.FLUSH | CBO.FLUSH (rs1) | I-Type | Zicbom | Performs a flush (clean + invalidate) operation on the cache block. |
| CBO.INVAL | CBO.INVAL (rs1) | I-Type | Zicbom | Performs an invalidate operation on the cache block. |
| CBO.ZERO | CBO.ZERO (rs1) | I-Type | Zicboz | Zeros a cache block corresponding to the address in rs1. |
| CLMUL | CLMUL rd, rs1, rs2 | R-Type | Zbc | Performs carry-less multiplication of the lower bits of rs1 and rs2. Used for CRC and GCM (crypto). |
| CLZ | CLZ rd, rs1 | I-Type | Zbb | Counts the number of 0 bits at the MSB end of the register. |
| CM.POP | CM.POP {reg_list}, stack_adj | Push/Pop | Zcmp | Pops multiple registers from the stack and restores sp. |
| CM.PUSH | CM.PUSH {reg_list}, -stack_adj | Push/Pop | Zcmp | Pushes multiple registers (ra, s0-s11) to the stack and adjusts sp. Critical for small code size. |
| CPOP | CPOP rd, rs1 | I-Type | Zbb | Counts the number of set bits (1s) in the register. |
| CSRC | CSRC csr, rs | I-Type | Pseudo | Clears bits in a CSR (bitwise AND NOT). |
| CSRR | CSRR rd, csr | I-Type | Pseudo | Reads the value of a CSR into a register. |
| CSRRC | CSRRC rd, csr, rs1 | I-Type | Zicsr | Reads the old value of the CSR, then clears bits in the CSR based on the mask in rs1. |
| CSRRCI | CSRRCI rd, csr, uimm | I-Type | Zicsr | Clears bits in a CSR using a 5-bit unsigned immediate. |
| CSRRS | CSRRS rd, csr, rs1 | I-Type | Zicsr | Reads the value of the CSR into rd, then bitwise ORs the value in rs1 into the CSR (setting bits). |
| CSRRSI | CSRRSI rd, csr, uimm | I-Type | Zicsr | Sets bits in a CSR using a 5-bit unsigned immediate. |
| CSRRW | CSRRW rd, csr, rs1 | I-Type | Zicsr | Atomically swaps values in the CSRs. Reads the old value of the CSR into rd, then writes rs1 to the CSR. |
| CSRRWI | CSRRWI rd, csr, uimm | I-Type | Zicsr | Updates a CSR using a 5-bit unsigned immediate (zimm) instead of a register. |
| CSRS | CSRS csr, rs | I-Type | Pseudo | Sets bits in a CSR (bitwise OR). |
| CSRW | CSRW csr, rs | I-Type | Pseudo | Writes a register value to a CSR. |
| CTZ | CTZ rd, rs1 | I-Type | Zbb | Counts the number of 0 bits at the LSB end of the register. |
| CZERO.EQZ | CZERO.EQZ rd, rs1, rs2 | R-Type | Zicond | Moves rs1 to rd if rs2 is non-zero, otherwise sets rd to zero. |
| CZERO.NEZ | CZERO.NEZ rd, rs1, rs2 | R-Type | Zicond | Moves rs1 to rd if rs2 is zero, otherwise sets rd to zero. |
| DIV | DIV rd, rs1, rs2 | R-Type | M | Performs signed integer division. |
| DIVU | DIVU rd, rs1, rs2 | R-Type | M | Performs unsigned integer division. |
| DIVUW | DIVUW rd, rs1, rs2 | R-Type | M | Performs 32-bit unsigned division of rs1 by rs2, sign-extending the result. |
| DIVW | DIVW rd, rs1, rs2 | R-Type | M | Performs 32-bit signed division of rs1 by rs2, sign-extending the result. |
| DRET | DRET | R-Type (System) | Privileged | Returns from Debug Mode to the mode defined in the 'dcsr' register. |
| EBREAK | EBREAK | I-Type | RV32I | Used by debuggers to cause control to be transferred back to a debugging environment. |
| ECALL | ECALL | I-Type | RV32I | Generates an environment call exception (system call). |
| FADD.D | FADD.D rd, rs1, rs2 | R-Type | D | Performs double-precision floating-point addition. |
| FADD.H | FADD.H rd, rs1, rs2 | R-Type | Zfh | Performs 16-bit floating-point addition. |
| FADD.S | FADD.S rd, rs1, rs2 | R-Type | F | Performs single-precision floating-point addition. |
| FCLASS.D | FCLASS.D rd, rs1 | R-Type | D | Examines a double-precision register and generates a classification bitmask. |
| FCLASS.H | FCLASS.H rd, rs1 | R-Type | Zfh | Examines a 16-bit floating-point number and generates a classification bitmask. |
| FCLASS.S | FCLASS.S rd, rs1 | R-Type | F | Examines the value in a float register and generates a 10-bit bitmask indicating its class (NaN, Inf, Zero, Normal, etc.). |
| FCVT.D.L | FCVT.D.L rd, rs1 | I-Type (Float) | D | Converts a 64-bit signed integer to a double-precision float. |
| FCVT.D.LU | FCVT.D.LU rd, rs1 | I-Type (Float) | D | Converts a 64-bit unsigned integer to a double-precision float. |
| FCVT.D.S | FCVT.D.S rd, rs1 | I-Type (Float) | D | Converts a single-precision float to a double-precision float. |
| FCVT.D.W | FCVT.D.W rd, rs1 | I-Type (Float) | D | Converts a 32-bit signed integer to a double-precision float. |
| FCVT.D.WU | FCVT.D.WU rd, rs1 | I-Type (Float) | D | Converts a 32-bit unsigned integer to a double-precision float. |
| FCVT.H.S | FCVT.H.S rd, rs1 | I-Type (Float) | Zfh | Converts a 32-bit single-precision float to a 16-bit half-precision float. |
| FCVT.H.W | FCVT.H.W rd, rs1 | I-Type (Float) | Zfh | Converts a 32-bit signed integer to a 16-bit floating-point number. |
| FCVT.H.WU | FCVT.H.WU rd, rs1 | I-Type (Float) | Zfh | Converts a 32-bit unsigned integer to a 16-bit floating-point number. |
| FCVT.L.D | FCVT.L.D rd, rs1 | I-Type (Float) | D | Converts a double-precision float to a 64-bit signed integer. |
| FCVT.L.S | FCVT.L.S rd, rs1 | I-Type (Float) | F | Converts a single-precision float to a 64-bit signed integer. |
| FCVT.LU.D | FCVT.LU.D rd, rs1 | I-Type (Float) | D | Converts a double-precision float to a 64-bit unsigned integer. |
| FCVT.LU.S | FCVT.LU.S rd, rs1 | I-Type (Float) | F | Converts a single-precision float to a 64-bit unsigned integer. |
| FCVT.S.D | FCVT.S.D rd, rs1 | I-Type (Float) | D | Converts a double-precision float to a single-precision float. |
| FCVT.S.H | FCVT.S.H rd, rs1 | I-Type (Float) | Zfh | Converts a 16-bit half-precision float to a 32-bit single-precision float. |
| FCVT.S.L | FCVT.S.L rd, rs1 | I-Type (Float) | F | Converts a 64-bit signed integer (Long) to a single-precision float. |
| FCVT.S.LU | FCVT.S.LU rd, rs1 | I-Type (Float) | F | Converts a 64-bit unsigned integer to a single-precision float. |
| FCVT.S.W | FCVT.S.W rd, rs1 | I-Type (Float) | F | Converts a signed 32-bit integer to a single-precision floating-point number. |
| FCVT.S.WU | FCVT.S.WU rd, rs1 | I-Type (Float) | F | Converts a 32-bit unsigned integer to a single-precision float. |
| FCVT.W.D | FCVT.W.D rd, rs1 | I-Type (Float) | D | Converts a double-precision float to a 32-bit signed integer. |
| FCVT.W.H | FCVT.W.H rd, rs1 | I-Type (Float) | Zfh | Converts a 16-bit floating-point number to a 32-bit signed integer. |
| FCVT.W.S | FCVT.W.S rd, rs1 | I-Type (Float) | F | Converts a single-precision floating-point number to a signed 32-bit integer. |
| FCVT.WU.D | FCVT.WU.D rd, rs1 | I-Type (Float) | D | Converts a double-precision float to a 32-bit unsigned integer. |
| FCVT.WU.H | FCVT.WU.H rd, rs1 | I-Type (Float) | Zfh | Converts a 16-bit floating-point number to a 32-bit unsigned integer. |
| FCVT.WU.S | FCVT.WU.S rd, rs1 | I-Type (Float) | F | Converts a single-precision float to a 32-bit unsigned integer. |
| FDIV.D | FDIV.D rd, rs1, rs2 | R-Type | D | Performs double-precision floating-point division. |
| FDIV.H | FDIV.H rd, rs1, rs2 | R-Type | Zfh | Performs 16-bit floating-point division. |
| FDIV.S | FDIV.S rd, rs1, rs2 | R-Type | F | Performs single-precision floating-point division. |
| FENCE | FENCE pred, succ | I-Type | RV32I | Orders device I/O and memory accesses. |
| FENCE.I | FENCE.I | I-Type | Zifencei | Synchronizes the instruction cache with the data cache (used after self-modifying code). |
| FEQ.D | FEQ.D rd, rs1, rs2 | R-Type | D | Sets integer rd to 1 if double rs1 equals double rs2, else 0. |
| FEQ.H | FEQ.H rd, rs1, rs2 | R-Type | Zfh | Sets integer rd to 1 if half-precision rs1 equals rs2, else 0. |
| FEQ.S | FEQ.S rd, rs1, rs2 | R-Type | F | Sets integer rd to 1 if float rs1 equals float rs2, else 0. |
| FLD | FLD rd, offset(rs1) | I-Type | D | Loads a 64-bit double-precision floating-point value from memory. |
| FLE.D | FLE.D rd, rs1, rs2 | R-Type | D | Sets integer rd to 1 if double rs1 is less than or equal to double rs2, else 0. |
| FLE.H | FLE.H rd, rs1, rs2 | R-Type | Zfh | Sets integer rd to 1 if half-precision rs1 is less than or equal to rs2, else 0. |
| FLE.S | FLE.S rd, rs1, rs2 | R-Type | F | Sets integer rd to 1 if float rs1 is less than or equal to float rs2, else 0. |
| FLH | FLH rd, offset(rs1) | I-Type | Zfh | Loads a 16-bit half-precision float from memory. |
| FLI.D | FLI.D rd, rs1 | R-Type | Zfa | Loads a common double-precision constant into a register. |
| FLI.H | FLI.H rd, rs1 | R-Type | Zfa | Loads a common half-precision constant into a register. |
| FLI.S | FLI.S rd, rs1 | R-Type | Zfa | Loads a common floating-point constant (e.g., 1.0, 0.5, PI) into a register from a small table. |
| FLT.D | FLT.D rd, rs1, rs2 | R-Type | D | Sets integer rd to 1 if double rs1 is less than double rs2, else 0. |
| FLT.H | FLT.H rd, rs1, rs2 | R-Type | Zfh | Sets integer rd to 1 if half-precision rs1 is less than rs2, else 0. |
| FLT.S | FLT.S rd, rs1, rs2 | R-Type | F | Sets integer rd to 1 if float rs1 is less than float rs2, else 0. |
| FLW | FLW rd, offset(rs1) | I-Type | F | Loads a single-precision floating-point value from memory. |
| FMADD.D | FMADD.D rd, rs1, rs2, rs3 | R4-Type | D | Computes (rs1 * rs2) + rs3 with a single rounding (64-bit). |
| FMADD.H | FMADD.H rd, rs1, rs2, rs3 | R4-Type | Zfh | Computes (rs1 * rs2) + rs3 with single rounding (16-bit). |
| FMADD.S | FMADD.S rd, rs1, rs2, rs3 | R4-Type | F | Computes (rs1 * rs2) + rs3 with a single rounding. |
| FMAX.D | FMAX.D rd, rs1, rs2 | R-Type | D | Writes the larger of two double-precision floating-point values to rd. |
| FMAX.H | FMAX.H rd, rs1, rs2 | R-Type | Zfh | Writes the larger of two 16-bit floating-point values to rd. |
| FMAX.S | FMAX.S rd, rs1, rs2 | R-Type | F | Writes the larger of two single-precision floating-point values to rd. |
| FMAXM.S | FMAXM.S rd, rs1, rs2 | R-Type | Zfa | Maximum of two floats, treating +0.0 as larger than -0.0. |
| FMIN.D | FMIN.D rd, rs1, rs2 | R-Type | D | Writes the smaller of two double-precision floating-point values to rd. |
| FMIN.H | FMIN.H rd, rs1, rs2 | R-Type | Zfh | Writes the smaller of two 16-bit floating-point values to rd. |
| FMIN.S | FMIN.S rd, rs1, rs2 | R-Type | F | Writes the smaller of two single-precision floating-point values to rd. |
| FMINM.S | FMINM.S rd, rs1, rs2 | R-Type | Zfa | Minimum of two floats, treating -0.0 as smaller than +0.0 (canonicalize NaNs). |
| FMSUB.D | FMSUB.D rd, rs1, rs2, rs3 | R4-Type | D | Computes (rs1 * rs2) - rs3 with a single rounding (Double). |
| FMSUB.H | FMSUB.H rd, rs1, rs2, rs3 | R4-Type | Zfh | Computes (rs1 * rs2) - rs3 with single rounding (16-bit). |
| FMSUB.S | FMSUB.S rd, rs1, rs2, rs3 | R4-Type | F | Computes (rs1 * rs2) - rs3 with a single rounding. |
| FMUL.D | FMUL.D rd, rs1, rs2 | R-Type | D | Performs double-precision floating-point multiplication. |
| FMUL.H | FMUL.H rd, rs1, rs2 | R-Type | Zfh | Performs 16-bit floating-point multiplication. |
| FMUL.S | FMUL.S rd, rs1, rs2 | R-Type | F | Performs single-precision floating-point multiplication. |
| FMV.D.X | FMV.D.X rd, rs1 | I-Type (Float) | D | Moves the bit pattern of a 64-bit integer register to a floating-point register (RV64). |
| FMV.W.X | FMV.W.X rd, rs1 | I-Type (Float) | F | Moves the bit pattern of an integer register to a floating-point register. |
| FMV.X.D | FMV.X.D rd, rs1 | I-Type (Float) | D | Moves the bit pattern of a 64-bit floating-point register to an integer register (RV64). |
| FMV.X.W | FMV.X.W rd, rs1 | I-Type (Float) | F | Moves the bit pattern of a floating-point register to an integer register. |
| FNMADD.D | FNMADD.D rd, rs1, rs2, rs3 | R4-Type | D | Computes -(rs1 * rs2) - rs3 with a single rounding (Double). |
| FNMADD.H | FNMADD.H rd, rs1, rs2, rs3 | R4-Type | Zfh | Computes -(rs1 * rs2) - rs3 with single rounding (16-bit). |
| FNMADD.S | FNMADD.S rd, rs1, rs2, rs3 | R4-Type | F | Computes -(rs1 * rs2) - rs3 with a single rounding. |
| FNMSUB.D | FNMSUB.D rd, rs1, rs2, rs3 | R4-Type | D | Computes -(rs1 * rs2) + rs3 with a single rounding (Double). |
| FNMSUB.H | FNMSUB.H rd, rs1, rs2, rs3 | R4-Type | Zfh | Computes -(rs1 * rs2) + rs3 with single rounding (16-bit). |
| FNMSUB.S | FNMSUB.S rd, rs1, rs2, rs3 | R4-Type | F | Computes -(rs1 * rs2) + rs3 with a single rounding. |
| FROUND.S | FROUND.S rd, rs1, rm | I-Type | Zfa | Rounds a float to the nearest integer value (returned as a float). |
| FSD | FSD rs2, offset(rs1) | S-Type | D | Stores a 64-bit double-precision floating-point value to memory. |
| FSGNJ.D | FSGNJ.D rd, rs1, rs2 | R-Type | D | Injects the sign of rs2 into rs1 (Double Precision). |
| FSGNJ.H | FSGNJ.H rd, rs1, rs2 | R-Type | Zfh | Injects the sign of rs2 into rs1 (16-bit). |
| FSGNJ.S | FSGNJ.S rd, rs1, rs2 | R-Type | F | Injects the sign of rs2 into rs1. Used to copy values or manipulate signs. |
| FSGNJN.D | FSGNJN.D rd, rs1, rs2 | R-Type | D | Injects the *negated* sign of rs2 into rs1 (Double Precision). |
| FSGNJN.H | FSGNJN.H rd, rs1, rs2 | R-Type | Zfh | Injects the negated sign of rs2 into rs1 (16-bit). |
| FSGNJN.S | FSGNJN.S rd, rs1, rs2 | R-Type | F | Injects the *negated* sign of rs2 into rs1. Used for negation and absolute value. |
| FSGNJX.D | FSGNJX.D rd, rs1, rs2 | R-Type | D | Injects the XOR of signs of rs1 and rs2 (Double Precision). |
| FSGNJX.H | FSGNJX.H rd, rs1, rs2 | R-Type | Zfh | Injects the XOR of signs of rs1 and rs2 (16-bit). |
| FSGNJX.S | FSGNJX.S rd, rs1, rs2 | R-Type | F | Injects the XOR of signs of rs1 and rs2. Used to copy sign. |
| FSH | FSH rs2, offset(rs1) | S-Type | Zfh | Stores a 16-bit half-precision float to memory. |
| FSQRT.D | FSQRT.D rd, rs1 | I-Type (Float) | D | Computes the square root of a double-precision floating-point number. |
| FSQRT.H | FSQRT.H rd, rs1 | I-Type (Float) | Zfh | Computes the square root of a 16-bit floating-point number. |
| FSQRT.S | FSQRT.S rd, rs1 | I-Type (Float) | F | Computes the square root of a single-precision floating-point number. |
| FSUB.D | FSUB.D rd, rs1, rs2 | R-Type | D | Performs double-precision floating-point subtraction. |
| FSUB.H | FSUB.H rd, rs1, rs2 | R-Type | Zfh | Performs 16-bit floating-point subtraction. |
| FSUB.S | FSUB.S rd, rs1, rs2 | R-Type | F | Performs single-precision floating-point subtraction. |
| FSW | FSW rs2, offset(rs1) | S-Type | F | Stores a single-precision floating-point value to memory. |
| HFENCE.GVMA | HFENCE.GVMA rs1, rs2 | R-Type | H | Synchronizes updates to guest physical address translation data structures. |
| HFENCE.VVMA | HFENCE.VVMA rs1, rs2 | R-Type | H | Synchronizes updates to VS-stage address translation data structures. |
| HLV.B | HLV.B rd, (rs1) | R-Type (System) | H | Loads a byte from Guest Physical Memory (VS-stage translation only). |
| HLV.D | HLV.D rd, (rs1) | R-Type (System) | H | Loads a doubleword from guest physical memory. |
| HLV.W | HLV.W rd, (rs1) | R-Type (System) | H | Loads a word from Guest Physical Memory (VS-stage translation only). |
| HLV.WU | HLV.WU rd, (rs1) | R-Type (System) | H | Loads a word from guest physical memory (unsigned). |
| HSV.B | HSV.B rs2, (rs1) | R-Type (System) | H | Stores a byte to Guest Physical Memory. |
| HSV.D | HSV.D rs2, (rs1) | R-Type (System) | H | Stores a doubleword to guest physical memory. |
| HSV.W | HSV.W rs2, (rs1) | R-Type (System) | H | Stores a word to Guest Physical Memory. |
| J | J offset | J-Type | Pseudo | Unconditionally jumps to a target offset. |
| JAL | JAL rd, offset | J-Type | RV32I | Jumps to an offset relative to PC and saves the return address (PC+4) to rd. |
| JALR | JALR rd, offset(rs1) | I-Type | RV32I | Jumps to address in rs1 + offset, saving return address to rd. |
| JR | JR rs | I-Type | Pseudo | Unconditionally jumps to an address held in a register. |
| LB | LB rd, offset(rs1) | I-Type | RV32I | Loads an 8-bit byte from memory and sign-extends it to the register width. |
| LBU | LBU rd, offset(rs1) | I-Type | RV32I | Loads an 8-bit byte from memory and zero-extends it. |
| LD | LD rd, offset(rs1) | I-Type | RV64I | Loads a 64-bit doubleword from memory. |
| LH | LH rd, offset(rs1) | I-Type | RV32I | Loads a 16-bit halfword from memory and sign-extends it. |
| LHU | LHU rd, offset(rs1) | I-Type | RV32I | Loads a 16-bit halfword from memory and zero-extends it. |
| LI | LI rd, imm | U-Type | Pseudo | Loads an arbitrary immediate value into a register. |
| LR.D | LR.D rd, (rs1) | R-Type (Atomic) | A | Loads a doubleword from memory and registers a reservation set. |
| LR.W | LR.W rd, (rs1) | R-Type (Atomic) | A | Loads a word from memory and registers a reservation set for the address. |
| LUI | LUI rd, imm | U-Type | RV32I | Loads the 20-bit immediate into the upper 20 bits of the register (lower 12 bits are zero). |
| LW | LW rd, offset(rs1) | I-Type | RV32I | Loads a 32-bit word from memory and sign-extends it to 64 bits. |
| LWU | LWU rd, offset(rs1) | I-Type | RV64I | Loads a 32-bit word from memory and zero-extends it to 64 bits. |
| MAX | MAX rd, rs1, rs2 | R-Type | Zbb | Computes the signed maximum of two registers. |
| MAXU | MAXU rd, rs1, rs2 | R-Type | Zbb | Computes the maximum of two unsigned integers. |
| MIN | MIN rd, rs1, rs2 | R-Type | Zbb | Computes the signed minimum of two registers. |
| MINU | MINU rd, rs1, rs2 | R-Type | Zbb | Computes the minimum of two unsigned integers. |
| MRET | MRET | R-Type (System) | Privileged | Returns from a machine-mode trap handler. |
| MUL | MUL rd, rs1, rs2 | R-Type | M | Performs a 32-bit (or 64-bit) multiplication of rs1 and rs2 and stores the lower bits in rd. |
| MULH | MULH rd, rs1, rs2 | R-Type | M | Performs a signed multiplication and stores the upper bits of the result. |
| MULHSU | MULHSU rd, rs1, rs2 | R-Type | M | Multiplies signed rs1 by unsigned rs2 and returns the upper XLEN bits. |
| MULHU | MULHU rd, rs1, rs2 | R-Type | M | Performs unsigned multiplication and returns the upper XLEN bits. |
| MULW | MULW rd, rs1, rs2 | R-Type | M | Performs 32-bit multiplication of rs1 and rs2, sign-extending the 32-bit result to 64 bits. |
| MV | MV rd, rs | I-Type | Pseudo | Copies the value of one register into another. |
| NEG | NEG rd, rs | R-Type | Pseudo | Computes the two's complement negation (arithmetic negative). |
| NOP | NOP | I-Type | Pseudo | Performs no operation. Used for alignment or timing delays. |
| NOT | NOT rd, rs | I-Type | Pseudo | Computes the bitwise logical negation (one's complement). |
| NTL.ALL | NTL.ALL | R-Type | Zihintntl | Hint that the subsequent store should bypass all cache levels. |
| NTL.P1 | NTL.P1 | R-Type | Zihintntl | Hint that the target cache block will be needed, but is likely to be discarded after use (Stream data). |
| NTL.PALL | NTL.PALL | R-Type | Zihintntl | Hint that the target data should not be cached in any level of the cache hierarchy (Transient data). |
| NTL.S1 | NTL.S1 | R-Type | Zihintntl | Hint that the subsequent store is non-temporal (Streaming Store). |
| OR | OR rd, rs1, rs2 | R-Type | RV32I | Performs a bitwise logical OR operation. |
| ORC.B | ORC.B rd, rs1 | I-Type | Zbb | Sets each byte of the result to 0xFF if the corresponding byte of the source is non-zero, else 0x00. |
| ORI | ORI rd, rs1, imm | I-Type | RV32I | Performs a bitwise logical OR with a sign-extended immediate. |
| ORN | ORN rd, rs1, rs2 | R-Type | Zbb | Performs bitwise OR with the bitwise negation of rs2 (rs1 | ~rs2). |
| PACK | PACK rd, rs1, rs2 | R-Type | Zbkb | Packs the lower halves of rs1 and rs2 into rd. |
| PACKH | PACKH rd, rs1, rs2 | R-Type | Zbkb | Packs the lower bytes of rs1 and rs2 into a 16-bit value. |
| PAUSE | PAUSE | I-Type (Hint) | Zihintpause | Hints that the current hart is in a spin-wait loop, allowing the hardware to reduce power consumption or yield resources. |
| PREFETCH.I | PREFETCH.I offset(rs1) | S-Type (Hint) | Zicbop | Hints to hardware to bring the cache block containing the instruction at the address into the instruction cache. |
| PREFETCH.R | PREFETCH.R offset(rs1) | S-Type (Hint) | Zicbop | Hints to hardware to bring the cache block at the address into the data cache for reading. |
| PREFETCH.W | PREFETCH.W offset(rs1) | S-Type (Hint) | Zicbop | Hints to hardware to bring the cache block at the address into the data cache for writing (exclusive ownership). |
| RDCYCLE | RDCYCLE rd | I-Type | Pseudo | Reads the lower 32/64 bits of the cycle counter. |
| RDINSTRET | RDINSTRET rd | I-Type | Pseudo | Reads the count of instructions retired (completed). |
| RDTIME | RDTIME rd | I-Type | Pseudo | Reads the lower 32/64 bits of the real-time clock. |
| REM | REM rd, rs1, rs2 | R-Type | M | Computes the signed remainder of division. |
| REMU | REMU rd, rs1, rs2 | R-Type | M | Computes the unsigned remainder of division. |
| REMUW | REMUW rd, rs1, rs2 | R-Type | M | Computes the remainder of 32-bit unsigned division, sign-extending the result. |
| REMW | REMW rd, rs1, rs2 | R-Type | M | Computes the remainder of 32-bit signed division, sign-extending the result. |
| RET | RET | I-Type | Pseudo | Returns from a subroutine call. |
| REV8 | REV8 rd, rs1 | I-Type | Zbb | Reverses the order of bytes in a register (Endian swap). |
| ROL | ROL rd, rs1, rs2 | R-Type | Zbb | Rotates the bits in rs1 left by the amount in rs2. |
| ROR | ROR rd, rs1, rs2 | R-Type | Zbb | Rotates the bits in rs1 right by the amount in rs2. |
| SB | SB rs2, offset(rs1) | S-Type | RV32I | Stores the lowest 8 bits of a register to memory. |
| SC.D | SC.D rd, rs2, (rs1) | R-Type (Atomic) | A | Conditionally stores a 64-bit value to memory if the reservation is valid. |
| SC.W | SC.W rd, rs2, (rs1) | R-Type (Atomic) | A | Conditionally stores a word to memory if the reservation (from LR) is still valid. |
| SD | SD rs2, offset(rs1) | S-Type | RV64I | Stores a 64-bit doubleword to memory. |
| SEQZ | SEQZ rd, rs | I-Type | Pseudo | Sets rd to 1 if rs is zero, otherwise 0. |
| SEX.B | SEX.B rd, rs1 | I-Type | Zbb | Sign-extends the lowest byte (8 bits) to XLEN bits. |
| SEX.H | SEX.H rd, rs1 | I-Type | Zbb | Sign-extends the lowest halfword (16 bits) to XLEN bits. |
| SFENCE.INVAL.IR | SFENCE.INVAL.IR | R-Type (System) | Svinval | Invalidates a range of address translations based on ASID and Virtual Address. |
| SFENCE.VMA | SFENCE.VMA rs1, rs2 | R-Type (System) | Privileged | Synchronizes updates to in-memory address translation data structures (TLB flush). |
| SFENCE.W.INVAL | SFENCE.W.INVAL | R-Type (System) | Svinval | Orders previous stores against subsequent local instruction fetches or translations (Memory Management). |
| SH | SH rs2, offset(rs1) | S-Type | RV32I | Stores the lowest 16 bits of a register to memory. |
| SH1ADD | SH1ADD rd, rs1, rs2 | R-Type | Zba | Shifts rs1 left by 1 and adds rs2. Used for calculating addresses of 16-bit elements. |
| SH2ADD | SH2ADD rd, rs1, rs2 | R-Type | Zba | Shifts rs1 left by 2 and adds rs2. Used for calculating addresses of 32-bit elements. |
| SH3ADD | SH3ADD rd, rs1, rs2 | R-Type | Zba | Shifts rs1 left by 3 and adds rs2. Used for calculating addresses of 64-bit elements. |
| SHA256SIG0 | SHA256SIG0 rd, rs1 | I-Type | Zk | Performs the Sigma0 transformation function for SHA-256. |
| SHA256SUM0 | SHA256SUM0 rd, rs1 | I-Type | Zk | Performs the Sum0 transformation function for SHA-256. |
| SHA512SIG0 | SHA512SIG0 rd, rs1 | R-Type | Zknh | Performs SHA-512 Sigma0 transformation (RV64). |
| SHA512SIG1 | SHA512SIG1 rd, rs1 | R-Type | Zknh | Performs SHA-512 Sigma1 transformation (RV64). |
| SHA512SUM0 | SHA512SUM0 rd, rs1 | R-Type | Zknh | Performs SHA-512 Sum0 transformation (RV64). |
| SHA512SUM1 | SHA512SUM1 rd, rs1 | R-Type | Zknh | Performs SHA-512 Sum1 transformation (RV64). |
| SLL | SLL rd, rs1, rs2 | R-Type | RV32I | Shifts a register left by the number of bits specified in another register. |
| SLLI | SLLI rd, rs1, shamt | I-Type (Shift) | RV32I | Shifts a register left by a constant amount. |
| SLLIW | SLLIW rd, rs1, shamt | I-Type (Shift) | RV64I | Shifts the lower 32 bits of rs1 left by a constant, sign-extending the result. |
| SLLW | SLLW rd, rs1, rs2 | R-Type | RV64I | Performs a 32-bit logical left shift on rs1 by the amount in rs2 (lower 5 bits), sign-extending the result. |
| SLT | SLT rd, rs1, rs2 | R-Type | RV32I | Sets rd to 1 if rs1 < rs2 (signed), otherwise 0. |
| SLTI | SLTI rd, rs1, imm | I-Type | RV32I | Sets rd to 1 if rs1 < immediate (signed), otherwise 0. |
| SLTIU | SLTIU rd, rs1, imm | I-Type | RV32I | Sets rd to 1 if rs1 < immediate (unsigned comparison), otherwise 0. |
| SLTU | SLTU rd, rs1, rs2 | R-Type | RV32I | Sets rd to 1 if rs1 < rs2 (unsigned comparison), otherwise 0. |
| SM3P0 | SM3P0 rd, rs1 | R-Type | Zksh | Performs the P0 permutation for the SM3 hash algorithm. |
| SM3P1 | SM3P1 rd, rs1 | R-Type | Zksh | Performs the P1 permutation for the SM3 hash algorithm. |
| SM4ED | SM4ED rd, rs1, rs2, bs | R-Type | Zksh | Accelerates the SM4 block cipher (encryption/decryption round). |
| SM4KS | SM4KS rd, rs1, rs2, bs | R-Type | Zksh | Accelerates the SM4 key schedule generation. |
| SNEZ | SNEZ rd, rs | R-Type | Pseudo | Sets rd to 1 if rs is not zero, otherwise 0. |
| SRA | SRA rd, rs1, rs2 | R-Type | RV32I | Shifts a register right, preserving the sign bit. |
| SRAIW | SRAIW rd, rs1, shamt | I-Type (Shift) | RV64I | Arithmetically shifts the lower 32 bits of rs1 right by a constant, sign-extending the result. |
| SRAW | SRAW rd, rs1, rs2 | R-Type | RV64I | Performs a 32-bit arithmetic right shift on rs1, sign-extending the result. |
| SRET | SRET | R-Type (System) | Privileged | Returns from a supervisor-mode trap handler. |
| SRL | SRL rd, rs1, rs2 | R-Type | RV32I | Shifts a register right, shifting in zeros. |
| SRLIW | SRLIW rd, rs1, shamt | I-Type (Shift) | RV64I | Logically shifts the lower 32 bits of rs1 right by a constant, sign-extending the result. |
| SRLW | SRLW rd, rs1, rs2 | R-Type | RV64I | Performs a 32-bit logical right shift on rs1 by the amount in rs2, sign-extending the result. |
| SUB | SUB rd, rs1, rs2 | R-Type | RV32I | Subtracts rs2 from rs1. |
| SUBW | SUBW rd, rs1, rs2 | R-Type | RV64I | Subtracts the lower 32 bits of rs2 from rs1 and sign-extends the result to 64 bits. |
| SW | SW rs2, offset(rs1) | S-Type | RV32I | Stores a 32-bit word to memory. |
| URET | URET | R-Type (System) | Privileged | Returns from a user-mode trap handler (requires N extension). |
| VAADD.VV | VAADD.VV vd, vs2, vs1, vm | OPIVV | V | Computes (vs1 + vs2) >> 1 with rounding. |
| VAADDU.VV | VAADDU.VV vd, vs2, vs1, vm | OPIVV | V | Computes (a + b + 1) >> 1 for unsigned integers. |
| VADC.VVM | VADC.VVM vd, vs2, vs1, v0 | OPIVV | V | Computes vd = vs1 + vs2 + carry (v0). |
| VADD.VI | VADD.VI vd, vs2, imm, vm | OPIVI | V | Adds immediate to vector. |
| VADD.VV | VADD.VV vd, vs2, vs1, vm | OPIVV | V | Adds elements of two vector registers. |
| VADDC.VVM | VADDC.VVM vd, vs2, vs1, v0 | OPIVV | V | Adds two vectors plus a carry-in from the mask register (v0). |
| VAESDF.VV | VAESDF.VV vd, vs2, vs1 | OPIVV | Zvkned | Performs the final AES decryption round. |
| VAESDM.VV | VAESDM.VV vd, vs2, vs1 | OPIVV | Zvkned | Performs a middle AES decryption round. |
| VAESEF.VV | VAESEF.VV vd, vs2, vs1 | OPIVV | Zvkned | Performs the final AES encryption round. |
| VAESEM.VV | VAESEM.VV vd, vs2, vs1 | OPIVV | Zvkned | Performs a middle AES encryption round. |
| VAESKF1.VI | VAESKF1.VI vd, vs2, uimm | OPIVI | Zvkned | Generates the next round key for AES (Step 1). |
| VAESKF2.VI | VAESKF2.VI vd, vs2, uimm | OPIVI | Zvkned | Generates the next round key for AES (Step 2). |
| VAMOADDD.V | VAMOADDD.V vd, (rs1), vs2, vm | VAMO | V | Atomically adds elements from vs2 to memory addresses (64-bit). |
| VAMOADDW.V | VAMOADDW.V vd, (rs1), vs2, vm | VAMO | V | Atomically adds elements from vs2 to memory addresses in rs1 (indexed by vs2? No, rs1 is base, vs2 is index). |
| VAMOANDD.V | VAMOANDD.V vd, (rs1), vs2, vm | VAMO | V | Atomically ANDs elements (64-bit). |
| VAMOANDW.V | VAMOANDW.V vd, (rs1), vs2, vm | VAMO | V | Atomically ANDs elements. |
| VAMOMAXD.V | VAMOMAXD.V vd, (rs1), vs2, vm | VAMO | V | Atomic Max (Signed, 64-bit). |
| VAMOMAXU.V | VAMOMAXU.V vd, (rs1), vs2, vm | VAMO | V | Atomic Max (Unsigned, Width implicit). |
| VAMOMAXW.V | VAMOMAXW.V vd, (rs1), vs2, vm | VAMO | V | Atomic Max (Signed). |
| VAMOMIND.V | VAMOMIND.V vd, (rs1), vs2, vm | VAMO | V | Atomic Min (Signed, 64-bit). |
| VAMOMINU.V | VAMOMINU.V vd, (rs1), vs2, vm | VAMO | V | Atomic Min (Unsigned, Width implicit). |
| VAMOMINW.V | VAMOMINW.V vd, (rs1), vs2, vm | VAMO | V | Atomic Min (Signed). |
| VAMOORD.V | VAMOORD.V vd, (rs1), vs2, vm | VAMO | V | Atomically ORs elements (64-bit). |
| VAMOORW.V | VAMOORW.V vd, (rs1), vs2, vm | VAMO | V | Atomically ORs elements. |
| VAMOXORD.V | VAMOXORD.V vd, (rs1), vs2, vm | VAMO | V | Atomically XORs elements (64-bit). |
| VAMOXORW.V | VAMOXORW.V vd, (rs1), vs2, vm | VAMO | V | Atomically XORs elements. |
| VAND.VI | VAND.VI vd, vs2, imm, vm | OPIVI | V | Bitwise AND with immediate. |
| VANDN.VV | VANDN.VV vd, vs2, vs1, vm | OPIVV | Zvbb | Computes vd = vs2 & ~vs1 (bitwise AND with inverted source). |
| VANDN.VX | VANDN.VX vd, vs2, rs1, vm | OPIVX | Zvbb | Computes vd = vs2 & ~rs1. |
| VASUB.VV | VASUB.VV vd, vs2, vs1, vm | OPIVV | V | Computes (a - b) >> 1 for signed integers. |
| VASUBU.VV | VASUBU.VV vd, vs2, vs1, vm | OPIVV | V | Computes (a - b) >> 1 for unsigned integers. |
| VBREV8.V | VBREV8.V vd, vs2, vm | OPIVV | Zvbb | Reverses the bits within each byte of the source elements. |
| VCLMUL.VV | VCLMUL.VV vd, vs2, vs1, vm | OPIVV | Zvbc | Performs carry-less multiplication on vector elements (GF(2^n)). |
| VCLMULH.VV | VCLMULH.VV vd, vs2, vs1, vm | OPIVV | Zvbc | Performs carry-less multiplication, keeping the high half. |
| VCLZ.V | VCLZ.V vd, vs2, vm | OPIVV | Zvbb | Counts the number of leading zero bits in each element. |
| VCOMPRESS.VM | VCOMPRESS.VM vd, vs2, vs1 | OPMVV | V | Compacts elements from source vector into contiguous elements in dest where the mask is 1. |
| VCPOP.M | VCPOP.M rd, vs2, vm | OPMVX | V | Counts set bits in the source mask register. |
| VCPOP.V | VCPOP.V vd, vs2, vm | OPIVV | Zvbb | Counts the number of set bits (1s) in each element. |
| VCTZ.V | VCTZ.V vd, vs2, vm | OPIVV | Zvbb | Counts the number of trailing zero bits in each element. |
| VDIV.VV | VDIV.VV vd, vs2, vs1, vm | OPIVV | V | Divides signed vector elements. |
| VDIVU.VV | VDIVU.VV vd, vs2, vs1, vm | OPIVV | V | Divides unsigned vector elements. |
| VFADD.VV | VFADD.VV vd, vs2, vs1, vm | OPFVV | V | Adds elements of two vector registers (Floating Point). |
| VFCLASS.V | VFCLASS.V vd, vs2, vm | OPFVV | V | Classifies elements of a float vector (NaN, Inf, etc.). |
| VFCVT.F.X.V | VFCVT.F.X.V vd, vs2, vm | OPFVV | V | Converts signed integer elements to floating-point. |
| VFCVT.X.F.V | VFCVT.X.F.V vd, vs2, vm | OPFVV | V | Converts floating-point elements to signed integers. |
| VFDIV.VV | VFDIV.VV vd, vs2, vs1, vm | OPFVV | V | Divides elements of two floating-point vectors. |
| VFIRST.M | VFIRST.M rd, vs2, vm | OPMVX | V | Finds the index of the first set bit in the mask. |
| VFMADD.VV | VFMADD.VV vd, vs1, vs2, vm | OPFVV | V | Computes (vs1 * vs2) + vd (overwriting vd) with single rounding. |
| VFMAX.VV | VFMAX.VV vd, vs2, vs1, vm | OPFVV | V | Writes the larger of two floating-point vector elements to vd. |
| VFMIN.VV | VFMIN.VV vd, vs2, vs1, vm | OPFVV | V | Writes the smaller of two floating-point vector elements to vd. |
| VFMUL.VV | VFMUL.VV vd, vs2, vs1, vm | OPFVV | V | Multiplies elements of two floating-point vectors. |
| VFMV.F.S | VFMV.F.S fd, vs2 | OPFVW | V | Moves element 0 of a float vector to a scalar float register. |
| VFMV.S.F | VFMV.S.F vd, fs1 | OPFVW | V | Moves a scalar float register to element 0 of a vector. |
| VFNCVT.F.F.W | VFNCVT.F.F.W vd, vs2, vm | OPFVV | V | Converts 2*N-bit floats to N-bit floats (e.g., FP32 -> FP16). |
| VFNCVT.X.F.W | VFNCVT.X.F.W vd, vs2, vm | OPFVV | V | Converts 2*N-bit float to N-bit signed integer. |
| VFREC7.V | VFREC7.V vd, vs2, vm | OPFVV | V | Computes an estimate of 1/x (7-bit precision). Used for fast division/normalization loops. |
| VFREDMAX.VS | VFREDMAX.VS vd, vs2, vs1, vm | OPFVV | V | Reduces a float vector to a scalar by finding the maximum element. |
| VFREDOSUM.VS | VFREDOSUM.VS vd, vs2, vs1, vm | OPFVV | V | Sums float vector elements in exact order (0 to vl-1). |
| VFREDUSUM.VS | VFREDUSUM.VS vd, vs2, vs1, vm | OPFVV | V | Reduces a float vector to a scalar by summing elements (Order not preserved, faster). |
| VFRSQRT7.V | VFRSQRT7.V vd, vs2, vm | OPFVV | V | Computes an estimate of 1/sqrt(x). Critical for vector normalization. |
| VFSGNJ.VV | VFSGNJ.VV vd, vs2, vs1, vm | OPFVV | V | Injects the sign of vs2 into vs1 (Copy Sign). |
| VFSQRT.V | VFSQRT.V vd, vs2, vm | OPFVV | V | Computes the square root of elements in a floating-point vector. |
| VFWADD.VV | VFWADD.VV vd, vs2, vs1, vm | OPFVV | V | Adds N-bit floats to produce 2*N-bit float results (e.g., FP16 + FP16 -> FP32). |
| VFWCVT.F.F.V | VFWCVT.F.F.V vd, vs2, vm | OPFVV | V | Converts N-bit floats to 2*N-bit floats (e.g., FP16 -> FP32). |
| VFWCVT.F.X.V | VFWCVT.F.X.V vd, vs2, vm | OPFVV | V | Converts N-bit integers to 2*N-bit floats (e.g., Int16 -> FP32). |
| VFWCVT.X.F.V | VFWCVT.X.F.V vd, vs2, vm | OPFVV | V | Converts N-bit float to 2*N-bit signed integer. |
| VFWMUL.VV | VFWMUL.VV vd, vs2, vs1, vm | OPFVV | V | Multiplies N-bit floats to produce 2*N-bit float results. |
| VFWREDOSUM.VS | VFWREDOSUM.VS vd, vs2, vs1, vm | OPFVV | V | Sums N-bit floats into 2*N-bit scalar accumulator (Ordered). |
| VFWREDUSUM.VS | VFWREDUSUM.VS vd, vs2, vs1, vm | OPFVV | V | Sums N-bit floats into 2*N-bit scalar accumulator (Unordered). |
| VGHSH.VV | VGHSH.VV vd, vs2, vs1 | OPIVV | Zvkg | Performs GHASH multiply-add for AES-GCM. |
| VGSHA.VV | VGSHA.VV vd, vs2, vs1 | OPIVV | Zvkg | Used in GCM GHASH loop. |
| VID.V | VID.V vd, vm | OPMVV | V | Writes the element index (0, 1, 2...) to the destination. |
| VIOTA.M | VIOTA.M vd, vs2, vm | OPMVV | V | Writes the index of the active element to the destination. Useful for parallel prefix sums. |
| VLE16.V | VLE16.V vd, (rs1), vm | VL-Type | V | Loads a vector of 16-bit elements from memory. |
| VLE16FF.V | VLE16FF.V vd, (rs1), vm | VL-Type | V | Loads 16-bit elements with fault suppression. |
| VLE32.V | VLE32.V vd, (rs1), vm | V-Load | V | Loads a vector of 32-bit elements from memory into a vector register. |
| VLE32FF.V | VLE32FF.V vd, (rs1), vm | VL-Type | V | Loads 32-bit elements with fault suppression. |
| VLE64.V | VLE64.V vd, (rs1), vm | VL-Type | V | Loads a vector of 64-bit elements from memory. |
| VLE64FF.V | VLE64FF.V vd, (rs1), vm | VL-Type | V | Loads 64-bit elements with fault suppression. |
| VLE8.V | VLE8.V vd, (rs1), vm | VL-Type | V | Loads a vector of 8-bit elements from memory. |
| VLE8FF.V | VLE8FF.V vd, (rs1), vm | VL-Type | V | Loads 8-bit elements, suppressing faults on elements after the first. Sets VL to number of elements loaded. Critical for strings. |
| VLM.V | VLM.V vd, (rs1) | VL-Type | V | Loads a vector mask register from memory. |
| VLOXEI32.V | VLOXEI32.V vd, (rs1), vs2, vm | VL-Type | V | Loads elements using indices, ensuring order (useful for I/O buffers). |
| VLSE32.V | VLSE32.V vd, (rs1), rs2, vm | VL-Type | V | Loads elements from memory with a fixed stride. |
| VLSEG2E16.V | VLSEG2E16.V vd, (rs1), vm | VL-Type | V | Loads 2 fields (e.g., Complex Real/Imag) of 16-bit elements. |
| VLSEG3E8.V | VLSEG3E8.V vd, (rs1), vm | VL-Type | V | Loads 3 fields (e.g., RGB) of 8-bit elements into 3 vector registers. |
| VLSEG4E8.V | VLSEG4E8.V vd, (rs1), vm | VL-Type | V | Loads 4 fields (e.g., RGBA) of 8-bit elements into 4 vector registers. |
| VLUXEI32.V | VLUXEI32.V vd, (rs1), vs2, vm | VL-Type | V | Loads elements from memory using a vector of indices (Gather). |
| VMACC.VV | VMACC.VV vd, vs1, vs2, vm | OPIVV | V | Computes vd = vd + (vs1 * vs2). Essential for dot products. |
| VMADC.VIM | VMADC.VIM vd, vs2, imm, v0 | OPIVI | V | Add Immediate with Carry. |
| VMADC.VVM | VMADC.VVM vd, vs2, vs1, v0 | OPIVV | V | Adds two vectors and a carry-in, producing the carry-out to the destination mask. |
| VMAND.MM | VMAND.MM vd, vs2, vs1 | OPMVV | V | Performs bitwise AND on vector mask registers. |
| VMANDN.MM | VMANDN.MM vd, vs2, vs1 | OPMVV | V | Computes vd = vs1 & ~vs2 (mask operation). |
| VMAX.VV | VMAX.VV vd, vs2, vs1, vm | OPIVV | V | Computes the signed maximum of elements in two vectors. |
| VMAXU.VV | VMAXU.VV vd, vs2, vs1, vm | OPIVV | V | Computes the unsigned maximum of elements in two vectors. |
| VMERGE.VIM | VMERGE.VIM vd, vs2, imm, v0 | OPIVI | V | Merges immediate vs vector based on mask. |
| VMERGE.VVM | VMERGE.VVM vd, vs2, vs1, v0 | OPIVV | V | Merges two vectors based on the mask (if mask=0, pick vs2; if mask=1, pick vs1). |
| VMERGE.VXM | VMERGE.VXM vd, vs2, rs1, v0 | OPIVX | V | Merges integer scalar vs vector based on mask. |
| VMFEQ.VV | VMFEQ.VV vd, vs2, vs1, vm | OPFVV | V | Compares float vectors for equality, writing result to mask register. |
| VMFLE.VV | VMFLE.VV vd, vs2, vs1, vm | OPFVV | V | Compares float vectors (vs2 <= vs1), writing result to mask register. |
| VMFLT.VV | VMFLT.VV vd, vs2, vs1, vm | OPFVV | V | Compares float vectors (vs2 < vs1), writing result to mask register. |
| VMIN.VV | VMIN.VV vd, vs2, vs1, vm | OPIVV | V | Computes the signed minimum of elements in two vectors. |
| VMINU.VV | VMINU.VV vd, vs2, vs1, vm | OPIVV | V | Computes the unsigned minimum of elements in two vectors. |
| VMNAND.MM | VMNAND.MM vd, vs2, vs1 | OPMVV | V | Performs bitwise NAND on vector mask registers. Used to invert masks (NOT). |
| VMORN.MM | VMORN.MM vd, vs2, vs1 | OPMVV | V | Computes vd = vs1 | ~vs2 (mask operation). |
| VMSBC.VV | VMSBC.VV vd, vs2, vs1 | OPMVV | V | Writes a mask where bits are 1 before the first element in vs2 that is 1. |
| VMSBF.M | VMSBF.M vd, vs2, vm | OPMVV | V | Sets mask bits before the first set bit in the source mask. |
| VMSEQ.VI | VMSEQ.VI vd, vs2, imm, vm | OPIVI | V | Sets mask if element == imm. |
| VMSEQ.VV | VMSEQ.VV vd, vs2, vs1, vm | OPIVV | V | Sets destination mask bit if elements are equal. |
| VMSGE.VV | VMSGE.VV vd, vs2, vs1, vm | OPIVV | V | Sets mask if vs2 >= vs1. |
| VMSGEU.VV | VMSGEU.VV vd, vs2, vs1, vm | OPIVV | V | Sets mask if vs2 >= vs1 (Unsigned). |
| VMSGT.VV | VMSGT.VV vd, vs2, vs1, vm | OPIVV | V | Sets mask if vs2 > vs1. |
| VMSGTU.VV | VMSGTU.VV vd, vs2, vs1, vm | OPIVV | V | Sets mask if vs2 > vs1 (Unsigned). |
| VMSIF.M | VMSIF.M vd, vs2, vm | OPMVV | V | Sets mask bits up to and including the first set bit in the source. |
| VMSLE.VI | VMSLE.VI vd, vs2, imm, vm | OPIVI | V | Sets mask if element <= imm (Signed). |
| VMSLE.VV | VMSLE.VV vd, vs2, vs1, vm | OPIVV | V | Sets mask if vs2 <= vs1. |
| VMSLEU.VI | VMSLEU.VI vd, vs2, imm, vm | OPIVI | V | Sets mask if element <= imm (Unsigned). |
| VMSLEU.VV | VMSLEU.VV vd, vs2, vs1, vm | OPIVV | V | Sets mask if vs2 <= vs1 (Unsigned). |
| VMSLT.VI | VMSLT.VI vd, vs2, imm, vm | OPIVI | V | Sets mask if element < imm (Signed). |
| VMSLT.VV | VMSLT.VV vd, vs2, vs1, vm | OPIVV | V | Sets destination mask bit if vs2 < vs1 (signed). |
| VMSLTU.VI | VMSLTU.VI vd, vs2, imm, vm | OPIVI | V | Sets mask if element < imm (Unsigned). |
| VMSLTU.VV | VMSLTU.VV vd, vs2, vs1, vm | OPIVV | V | Sets destination mask bit if vs2 < vs1 (unsigned). |
| VMSNE.VI | VMSNE.VI vd, vs2, imm, vm | OPIVI | V | Sets mask if element != imm. |
| VMSOF.M | VMSOF.M vd, vs2, vm | OPMVV | V | Sets only the first set bit from the source mask. |
| VMUL.VV | VMUL.VV vd, vs2, vs1, vm | OPIVV | V | Multiplies elements of two vector registers. |
| VMULH.VV | VMULH.VV vd, vs2, vs1, vm | OPIVV | V | Multiplies signed integers and keeps the high N bits. |
| VMULHU.VV | VMULHU.VV vd, vs2, vs1, vm | OPIVV | V | Multiplies unsigned integers and keeps the high N bits. |
| VMV.S.X | VMV.S.X vd, rs1 | OPMVX | V | Copies an integer register to element 0 of a vector. |
| VMV.V.V | VMV.V.V vd, vs1 | OPIVV | V | Copies a vector register. |
| VMV.X.S | VMV.X.S rd, vs2 | OPMVX | V | Copies element 0 of a vector to an integer register. |
| VMV1R.V | VMV1R.V vd, vs2 | OPVI | V | Moves a single vector register to another, ignoring VL and VTYPE (used for spilling). |
| VMV2R.V | VMV2R.V vd, vs2 | OPVI | V | Moves 2 consecutive vector registers, ignoring VL and VTYPE. |
| VMV4R.V | VMV4R.V vd, vs2 | OPVI | V | Moves 4 consecutive vector registers, ignoring VL and VTYPE. |
| VMV8R.V | VMV8R.V vd, vs2 | OPVI | V | Moves 8 consecutive vector registers, ignoring VL and VTYPE. |
| VMXNOR.MM | VMXNOR.MM vd, vs2, vs1 | OPMVV | V | Computes vd = ~(vs1 ^ vs2) (mask operation). |
| VNCLIP.WV | VNCLIP.WV vd, vs2, vs1, vm | OPIVV | V | Shifts elements right, rounds, and clips (saturates) the result to the destination width. Critical for Quantization. |
| VNCLIPU.WI | VNCLIPU.WI vd, vs2, imm, vm | OPIVI | V | Shifts right (logical), rounds, and clips to unsigned destination. Used for pixel packing. |
| VNMSUB.VV | VNMSUB.VV vd, vs1, vs2, vm | OPIVV | V | Computes vd = -(vd - (vs1 * vs2)). |
| VNSRA.WI | VNSRA.WI vd, vs2, imm, vm | OPIVI | V | Shifts wide elements right (arithmetic) by immediate and narrows. |
| VNSRA.WX | VNSRA.WX vd, vs2, rs1, vm | OPIVX | V | Arithmetically shifts 2*N-bit elements right and narrows to N-bits. |
| VNSRL.WI | VNSRL.WI vd, vs2, imm, vm | OPIVI | V | Shifts wide elements right by immediate and narrows. |
| VNSRL.WX | VNSRL.WX vd, vs2, rs1, vm | OPIVX | V | Shifts 2*N-bit elements right and narrows the result to N-bits. |
| VOR.VI | VOR.VI vd, vs2, imm, vm | OPIVI | V | Bitwise OR with immediate. |
| VOR.VV | VOR.VV vd, vs2, vs1, vm | OPIVV | V | Performs bitwise OR on elements of two vectors. |
| VORN.VV | VORN.VV vd, vs2, vs1, vm | OPIVV | Zvbb | Computes vd = vs2 | ~vs1 (bitwise OR with inverted source). |
| VORN.VX | VORN.VX vd, vs2, rs1, vm | OPIVX | Zvbb | Computes vd = vs2 | ~rs1. |
| VREDAND.VS | VREDAND.VS vd, vs2, vs1, vm | OPMVV | V | Reduces a vector to a scalar using bitwise AND. |
| VREDMAX.VS | VREDMAX.VS vd, vs2, vs1, vm | OPMVV | V | Reduces a vector to a scalar by finding the maximum signed element. |
| VREDMIN.VS | VREDMIN.VS vd, vs2, vs1, vm | OPMVV | V | Reduces a vector to a scalar by finding the minimum signed element. |
| VREDOR.VS | VREDOR.VS vd, vs2, vs1, vm | OPMVV | V | Reduces a vector to a scalar using bitwise OR. |
| VREDSUM.VS | VREDSUM.VS vd, vs2, vs1, vm | OPMVV | V | Reduces a vector to a scalar by summing all elements. |
| VREM.VV | VREM.VV vd, vs2, vs1, vm | OPIVV | V | Computes signed remainder. |
| VREMU.VV | VREMU.VV vd, vs2, vs1, vm | OPIVV | V | Computes unsigned remainder. |
| VREV8.V | VREV8.V vd, vs2, vm | OPIVV | Zvbb | Reverses the order of bytes within each element (Endian swap). |
| VRGATHER.VI | VRGATHER.VI vd, vs2, imm, vm | OPIVI | V | Gathers element at index 'imm' from vs2 (splat). |
| VRGATHER.VV | VRGATHER.VV vd, vs2, vs1, vm | OPIVV | V | Gathers elements from a vector register using indices from another vector register. |
| VROL.VV | VROL.VV vd, vs2, vs1, vm | OPIVV | Zvbb | Rotates bits in elements of vs2 left by amounts in vs1. |
| VROL.VX | VROL.VX vd, vs2, rs1, vm | OPIVX | Zvbb | Rotates bits in elements of vs2 left by scalar rs1. |
| VROR.VV | VROR.VV vd, vs2, vs1, vm | OPIVV | Zvbb | Rotates bits in elements of vs2 right by amounts in vs1. |
| VROR.VX | VROR.VX vd, vs2, rs1, vm | OPIVX | Zvbb | Rotates bits in elements of vs2 right by scalar rs1. |
| VRSUB.VI | VRSUB.VI vd, vs2, imm, vm | OPIVI | V | Computes vd = imm - vs2. |
| VRSUB.VX | VRSUB.VX vd, vs2, rs1, vm | OPIVX | V | Subtracts vector elements from a scalar value (scalar - vector). |
| VSADD.VV | VSADD.VV vd, vs2, vs1, vm | OPIVV | V | Adds elements with signed saturation (clips to Max/Min instead of wrapping). |
| VSADDU.VV | VSADDU.VV vd, vs2, vs1, vm | OPIVV | V | Adds unsigned integers with saturation (clips to max instead of wrapping). |
| VSBC.VVM | VSBC.VVM vd, vs2, vs1, v0 | OPIVV | V | Subtracts two vectors minus a borrow-in from the mask register. |
| VSE16.V | VSE16.V vs3, (rs1), vm | VS-Type | V | Stores a vector of 16-bit elements to memory. |
| VSE32.V | VSE32.V vs3, (rs1), vm | V-Store | V | Stores a vector of 32-bit elements from a vector register to memory. |
| VSE64.V | VSE64.V vs3, (rs1), vm | VS-Type | V | Stores a vector of 64-bit elements to memory. |
| VSE8.V | VSE8.V vs3, (rs1), vm | VS-Type | V | Stores a vector of 8-bit elements to memory. |
| VSETIVLI | VSETIVLI rd, uimm, vtypei | V-Type | V | Sets vector length (VL) and type (VTYPE) using a 5-bit immediate for the requested length. |
| VSETVL | VSETVL rd, rs1, rs2 | V-Type | V | Sets the vector length (VL) based on the application vector length (AVL) in rs1 and configuration in rs2. |
| VSETVLI | VSETVLI rd, rs1, vtypei | V-Type | V | Configures the vector length (vl) and vector type (vtype) based on application needs. |
| VSHA2CH.VV | VSHA2CH.VV vd, vs2, vs1 | OPIVV | Zvknha | Performs SHA-256 compression (high 128 bits). |
| VSHA2CL.VV | VSHA2CL.VV vd, vs2, vs1 | OPIVV | Zvknha | Performs SHA-256 compression (low 128 bits). |
| VSHA2MS.VV | VSHA2MS.VV vd, vs2, vs1 | OPIVV | Zvknha | Generates SHA-256 message schedule words. |
| VSLIDE1DOWN.VX | VSLIDE1DOWN.VX vd, vs2, rs1, vm | OPIVX | V | Moves elements down by 1, injecting scalar into top index. |
| VSLIDE1UP.VX | VSLIDE1UP.VX vd, vs2, rs1, vm | OPIVX | V | Moves elements up by 1, injecting scalar into index 0. |
| VSLIDEDOWN.VI | VSLIDEDOWN.VI vd, vs2, imm, vm | OPIVI | V | Moves elements down by immediate amount. |
| VSLIDEDOWN.VX | VSLIDEDOWN.VX vd, vs2, rs1, vm | OPIVX | V | Moves elements down by a scalar amount (vd[i] = vs2[i + rs1]). |
| VSLIDEUP.VI | VSLIDEUP.VI vd, vs2, imm, vm | OPIVI | V | Moves elements up by immediate amount. |
| VSLIDEUP.VX | VSLIDEUP.VX vd, vs2, rs1, vm | OPIVX | V | Moves elements up by a scalar amount (vd[i] = vs2[i - rs1]). |
| VSLL.VI | VSLL.VI vd, vs2, imm, vm | OPIVI | V | Shifts elements left by immediate. |
| VSLL.VV | VSLL.VV vd, vs2, vs1, vm | OPIVV | V | Shifts elements of vector vs2 left by amounts in vs1. |
| VSM.V | VSM.V vs3, (rs1) | VS-Type | V | Stores a vector mask register to memory. |
| VSMUL.VV | VSMUL.VV vd, vs2, vs1, vm | OPIVV | V | Performs signed saturating multiplication, keeping the high half of the product (Fixed-point support). |
| VSOXEI32.V | VSOXEI32.V vs3, (rs1), vs2, vm | VS-Type | V | Stores elements using indices, ensuring order. |
| VSRA.VI | VSRA.VI vd, vs2, imm, vm | OPIVI | V | Shifts elements right (arithmetic) by immediate. |
| VSRA.VV | VSRA.VV vd, vs2, vs1, vm | OPIVV | V | Shifts elements of vector vs2 right (arithmetic) by amounts in vs1. |
| VSRL.VI | VSRL.VI vd, vs2, imm, vm | OPIVI | V | Shifts elements right (logical) by immediate. |
| VSRL.VV | VSRL.VV vd, vs2, vs1, vm | OPIVV | V | Shifts elements of vector vs2 right (logical) by amounts in vs1. |
| VSSE32.V | VSSE32.V vs3, (rs1), rs2, vm | VS-Type | V | Stores elements to memory with a fixed stride. |
| VSSEG2E16.V | VSSEG2E16.V vs3, (rs1), vm | VS-Type | V | Stores 2 vector registers as interleaved 16-bit fields. |
| VSSEG3E8.V | VSSEG3E8.V vs3, (rs1), vm | VS-Type | V | Stores 3 vector registers (e.g., RGB) into memory as interleaved 8-bit fields. |
| VSSEG4E8.V | VSSEG4E8.V vs3, (rs1), vm | VS-Type | V | Stores 4 vector registers (e.g., RGBA) into memory as interleaved 8-bit fields. |
| VSSRA.VV | VSSRA.VV vd, vs2, vs1, vm | OPIVV | V | Shifts right with sign extension and rounding/saturation logic. |
| VSSRL.VV | VSSRL.VV vd, vs2, vs1, vm | OPIVV | V | Shifts right with zero extension and rounding/saturation logic. |
| VSSUB.VV | VSSUB.VV vd, vs2, vs1, vm | OPIVV | V | Subtracts elements with signed saturation. |
| VSSUBU.VV | VSSUBU.VV vd, vs2, vs1, vm | OPIVV | V | Subtracts unsigned integers with saturation (clips to 0 instead of wrapping). |
| VSUB.VV | VSUB.VV vd, vs2, vs1, vm | OPIVV | V | Subtracts elements of two vector registers. |
| VSUXEI32.V | VSUXEI32.V vs3, (rs1), vs2, vm | VS-Type | V | Stores elements to memory using a vector of indices (Scatter). |
| VWADD.VV | VWADD.VV vd, vs2, vs1, vm | OPIVV | V | Adds N-bit elements to produce 2*N-bit results (Widening). |
| VWADDU.VV | VWADDU.VV vd, vs2, vs1, vm | OPIVV | V | Adds unsigned N-bit elements to produce unsigned 2*N-bit results. |
| VWMACC.VV | VWMACC.VV vd, vs1, vs2, vm | OPIVV | V | Computes vd = vd + (vs1 * vs2) with widening (N*N -> 2N + 2N). |
| VWMACCSU.VV | VWMACCSU.VV vd, vs1, vs2, vm | OPIVV | V | vd = vd + (signed(vs1) * unsigned(vs2)). |
| VWMACCU.VV | VWMACCU.VV vd, vs1, vs2, vm | OPIVV | V | Computes vd = vd + (vs1 * vs2) widening unsigned. |
| VWMACCUS.VV | VWMACCUS.VV vd, vs1, vs2, vm | OPIVV | V | vd = vd + (unsigned(vs1) * signed(vs2)). |
| VWMUL.VV | VWMUL.VV vd, vs2, vs1, vm | OPIVV | V | Multiplies N-bit elements to produce 2*N-bit results. |
| VWREDSUM.VS | VWREDSUM.VS vd, vs2, vs1, vm | OPMVV | V | Sums N-bit elements into a 2*N-bit scalar accumulator (Signed). |
| VWREDSUMU.VS | VWREDSUMU.VS vd, vs2, vs1, vm | OPMVV | V | Sums N-bit elements into a 2*N-bit scalar accumulator (Unsigned). |
| VWSLL.VI | VWSLL.VI vd, vs2, imm, vm | OPIVI | Zvbb | Shifts elements left by immediate, widening the result. |
| VWSLL.VV | VWSLL.VV vd, vs2, vs1, vm | OPIVV | Zvbb | Shifts N-bit elements left to produce 2*N-bit results. |
| VWSLL.VX | VWSLL.VX vd, vs2, rs1, vm | OPIVX | Zvbb | Shifts elements left by scalar rs1, widening the result. |
| VWSUB.VV | VWSUB.VV vd, vs2, vs1, vm | OPIVV | V | Subtracts N-bit elements to produce 2*N-bit results. |
| VXNOR.VV | VXNOR.VV vd, vs2, vs1, vm | OPIVV | Zvbb | Computes vd = ~(vs2 ^ vs1) (bitwise Exclusive-NOR). |
| VXNOR.VX | VXNOR.VX vd, vs2, rs1, vm | OPIVX | Zvbb | Computes vd = ~(vs2 ^ rs1). |
| VXOR.VI | VXOR.VI vd, vs2, imm, vm | OPIVI | V | Bitwise XOR with immediate. |
| VXOR.VV | VXOR.VV vd, vs2, vs1, vm | OPIVV | V | Performs bitwise XOR on elements of two vectors. |
| WFI | WFI | R-Type (System) | Privileged | Provides a hint to the implementation that the current hart can be stalled until an interrupt occurs. |
| WRS.NTO | WRS.NTO | I-Type | Zawrs | Stalls the hart until a reservation set is invalid or a short timeout expires. Used for efficient polling/spinlocks. |
| WRS.STO | WRS.STO | I-Type | Zawrs | Stalls the hart until a reservation set is invalid or a very short implementation-defined timeout expires. |
| XNOR | XNOR rd, rs1, rs2 | R-Type | Zbb | Performs bitwise exclusive-NOR (rs1 ^ ~rs2). |
| XOR | XOR rd, rs1, rs2 | R-Type | RV32I | Performs a bitwise logical Exclusive-OR operation. |
| XORI | XORI rd, rs1, imm | I-Type | RV32I | Performs a bitwise logical Exclusive-OR with a sign-extended immediate. |
| ZEXT.H | ZEXT.H rd, rs1 | I-Type | Zbb | Zero-extends the lowest halfword (16 bits) to XLEN bits. |