VREDAND.VS

Vector Reduction AND

VREDAND.VS vd, vs2, vs1, vm

Reduces a vector to a scalar using bitwise AND.

Encoding

Binary Layout

000001

31:26

vm

25

vs2

24:20

vs1

19:15

010

14:12

vd

11:7

1010111

6:0

 

Format OPMVV

Opcode 0x04002057

Extension V

Operands

• vd
  Dest (Scalar)
• vs2
  Src Vector
• vs1
  Start Scalar

Example

VREDAND.VS v1, v4, v2, v0.t

Related

More in V

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

Performs a vector reduction: applies the operation across all active elements of vs2, using vs1[0] as the initial accumulator, and writes the scalar result to vd[0]. Active elements are determined by vl.

Operation

vd[0] = vs1[0] & reduce_and(vs2);