VMSLT.VV

Vector Mask Set Less Than (Signed)

VMSLT.VV vd, vs2, vs1, vm

Sets destination mask bit if vs2 < vs1 (signed).

Details

Compares elements element-wise for less than and writes a mask result to vd.

Pseudocode Operation

foreach(i < vl): vd[i] = (vs2[i] <s vs1[i]) ? 1 : 0;

Example

VMSLT.VV v1, v4, v2, v0.t

Encoding

Binary Layout
011011
31:26
vm
25
vs2
24:20
vs1
19:15
000
14:12
vd
11:7
1010111
6:0
 
Format OPIVV
Opcode 0x57
Extension V

Operands

  • vd
    Dest Mask
  • vs2
    Source vector register 2
  • vs1
    Source vector register 1