CSRRCI
CSR Read and Clear Immediate
CSRRCI rd, csr, uimm
Clears bits in a CSR using a 5-bit unsigned immediate.
Encoding
Binary Layout
csr
31:20
zimm5
19:15
111
14:12
rd
11:7
1110011
6:0
Operands
-
rd
Destination register (integer) -
csr
CSR Address -
uimm
Bit Mask
Example
CSRRCI x0, sstatus, 2
// Clears bit 1 of sstatus.
Related
More in Zicsr
Reference
View in RISC-V Unprivileged ISA Specification ↗
RISC-V ISA Manual
Description
CSRRCI atomically reads CSR csr into rd, then clears bits in the CSR corresponding to set bits in the zero-extended 5-bit immediate. If the immediate is zero, no bits are modified.
Operation
t = CSRs[csr]; CSRs[csr] = t & ~zext(uimm); R[rd] = t;