CSRRWI

CSR Read/Write Immediate

CSRRWI rd, csr, uimm

Updates a CSR using a 5-bit unsigned immediate (zimm) instead of a register.

Encoding

Binary Layout

csr

31:20

zimm5

19:15

101

14:12

rd

11:7

1110011

6:0

 

Format I-Type

Opcode 0x00005073

Extension Zicsr

Operands

• rd
  Destination register (integer)
• csr
  CSR Address
• uimm
  5-bit Unsigned Imm

Example

CSRRWI x0, 0x001, 0

// Writes 0 to CSR 0x001.

Related

More in Zicsr

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

CSRRWI atomically reads CSR csr into rd, then writes the zero-extended 5-bit immediate to the CSR. If rd is x0, the read is skipped.

Operation

t = CSRs[csr]; CSRs[csr] = zext(uimm); R[rd] = t;