CSRRS

Control Status Register Read and Set

CSRRS rd, csr, rs1

Reads the value of the CSR into rd, then bitwise ORs the value in rs1 into the CSR (setting bits).

Encoding

Binary Layout

csr

31:20

rs1

19:15

010

14:12

rd

11:7

1110011

6:0

 

Format I-Type

Opcode 0x00002073

Extension Zicsr

Operands

• rd
  Destination register (integer)
• csr
  CSR Address
• rs1
  Bit Mask

Example

CSRRS x0, sstatus, x5

// Sets bits in 'sstatus' using mask in x5 (Result discarded).

Related

More in Zicsr

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

CSRRS atomically reads CSR csr into rd, then sets the bits in the CSR that correspond to bits set in rs1. If rs1 is x0, no bits are modified.

Operation

t = CSRs[csr]; CSRs[csr] = t | R[rs1]; R[rd] = t;