RISC-V Opcode Map
Reverse lookup instructions by their hexadecimal encoding.
| Opcode | Mnemonic | Syntax | Format | Name |
|---|---|---|---|---|
| 0x33 | ADD | ADD rd, rs1, rs2 | R-Type | Add Integer |
| 0x13 | ADDI | ADDI rd, rs1, imm | I-Type | Add Immediate |
| 0x1B | ADDIW | ADDIW rd, rs1, imm | I-Type | Add Immediate Word |
| 0x3B | ADDUW | ADDUW rd, rs1, rs2 | R-Type | Add Unsigned Word |
| 0x3B | ADDW | ADDW rd, rs1, rs2 | R-Type | Add Word |
| 0x33 | AES64DS | AES64DS rd, rs1, rs2 | R-Type | AES-64 Decryption Schedule |
| 0x33 | AES64ES | AES64ES rd, rs1, rs2 | R-Type | AES-64 Encryption Schedule |
| 0x13 | AES64IM | AES64IM rd, rs1 | R-Type | AES-64 Inverse MixColumns |
| 0x13 | AES64KS1I | AES64KS1I rd, rs1, rcon | I-Type | AES-64 Key Schedule Instruction 1 |
| 0x33 | AES64KS2 | AES64KS2 rd, rs1, rs2 | R-Type | AES-64 Key Schedule Instruction 2 |
| 0x2F | AMOADD.D | AMOADD.D rd, rs2, (rs1) | R-Type (Atomic) | Atomic Add Doubleword |
| 0x2F | AMOADD.W | AMOADD.W rd, rs2, (rs1) | R-Type (Atomic) | Atomic Add Word |
| 0x2F | AMOAND.D | AMOAND.D rd, rs2, (rs1) | R-Type (Atomic) | Atomic AND Doubleword |
| 0x2F | AMOAND.W | AMOAND.W rd, rs2, (rs1) | R-Type (Atomic) | Atomic AND Word |
| 0x2F | AMOCAS.D | AMOCAS.D rd, rs2, (rs1) | R-Type (Atomic) | Atomic Compare and Swap Doubleword |
| 0x2F | AMOCAS.W | AMOCAS.W rd, rs2, (rs1) | R-Type (Atomic) | Atomic Compare and Swap Word |
| 0x2F | AMOMAX.D | AMOMAX.D rd, rs2, (rs1) | R-Type (Atomic) | Atomic Max Doubleword |
| 0x2F | AMOMAX.W | AMOMAX.W rd, rs2, (rs1) | R-Type (Atomic) | Atomic Max Word |
| 0x2F | AMOMAXU.D | AMOMAXU.D rd, rs2, (rs1) | R-Type (Atomic) | Atomic Max Unsigned Doubleword |
| 0x2F | AMOMAXU.W | AMOMAXU.W rd, rs2, (rs1) | R-Type (Atomic) | Atomic Max Unsigned Word |
| 0x2F | AMOMIN.D | AMOMIN.D rd, rs2, (rs1) | R-Type (Atomic) | Atomic Min Doubleword |
| 0x2F | AMOMIN.W | AMOMIN.W rd, rs2, (rs1) | R-Type (Atomic) | Atomic Min Word |
| 0x2F | AMOMINU.D | AMOMINU.D rd, rs2, (rs1) | R-Type (Atomic) | Atomic Min Unsigned Doubleword |
| 0x2F | AMOMINU.W | AMOMINU.W rd, rs2, (rs1) | R-Type (Atomic) | Atomic Min Unsigned Word |
| 0x2F | AMOOR.D | AMOOR.D rd, rs2, (rs1) | R-Type (Atomic) | Atomic OR Doubleword |
| 0x2F | AMOOR.W | AMOOR.W rd, rs2, (rs1) | R-Type (Atomic) | Atomic OR Word |
| 0x2F | AMOSWAP.D | AMOSWAP.D rd, rs2, (rs1) | R-Type (Atomic) | Atomic Swap Doubleword |
| 0x2F | AMOSWAP.W | AMOSWAP.W rd, rs2, (rs1) | R-Type (Atomic) | Atomic Swap Word |
| 0x2F | AMOXOR.D | AMOXOR.D rd, rs2, (rs1) | R-Type (Atomic) | Atomic XOR Doubleword |
| 0x2F | AMOXOR.W | AMOXOR.W rd, rs2, (rs1) | R-Type (Atomic) | Atomic XOR Word |
| 0x33 | AND | AND rd, rs1, rs2 | R-Type | Logical AND |
| 0x13 | ANDI | ANDI rd, rs1, imm | I-Type | Logical AND Immediate |
| 0x33 | ANDN | ANDN rd, rs1, rs2 | R-Type | AND Not |
| 0x17 | AUIPC | AUIPC rd, imm | U-Type | Add Upper Immediate to PC |
| 0x33 | BCLR | BCLR rd, rs1, rs2 | R-Type | Bit Clear |
| 0x13 | BCLRI | BCLRI rd, rs1, imm | I-Type | Bit Clear Immediate |
| 0x63 | BEQ | BEQ rs1, rs2, offset | B-Type | Branch if Equal |
| 0x63 | BEQZ | BEQZ rs, offset | B-Type | Branch if Equal to Zero |
| 0x33 | BEXT | BEXT rd, rs1, rs2 | R-Type | Bit Extract |
| 0x13 | BEXTI | BEXTI rd, rs1, imm | I-Type | Bit Extract Immediate |
| 0x63 | BGE | BGE rs1, rs2, offset | B-Type | Branch if Greater or Equal |
| 0x63 | BGEU | BGEU rs1, rs2, offset | B-Type | Branch if Greater or Equal Unsigned |
| 0x33 | BINV | BINV rd, rs1, rs2 | R-Type | Bit Invert |
| 0x13 | BINVI | BINVI rd, rs1, imm | I-Type | Bit Invert Immediate |
| 0x63 | BLT | BLT rs1, rs2, offset | B-Type | Branch if Less Than |
| 0x63 | BLTU | BLTU rs1, rs2, offset | B-Type | Branch if Less Than Unsigned |
| 0x63 | BNE | BNE rs1, rs2, offset | B-Type | Branch if Not Equal |
| 0x63 | BNEZ | BNEZ rs, offset | B-Type | Branch if Not Equal to Zero |
| 0x33 | BSET | BSET rd, rs1, rs2 | R-Type | Bit Set |
| 0x13 | BSETI | BSETI rd, rs1, imm | I-Type | Bit Set Immediate |
| 02 | C.ADD | C.ADD rd, rs2 | CR | Compressed Add |
| 01 | C.ADDI | C.ADDI rd, imm | CI | Compressed Add Immediate |
| 01 | C.ADDI16SP | C.ADDI16SP imm | CI | Compressed Add Immediate to Stack Pointer |
| 00 | C.ADDI4SPN | C.ADDI4SPN rd', uimm | CIW | Compressed Add Immediate to Stack Pointer (Non-zero) |
| 01 | C.ADDIW | C.ADDIW rd, imm | CI | Compressed Add Immediate Word |
| 01 | C.ADDW | C.ADDW rd', rs2' | CA | Compressed Add Word |
| 01 | C.AND | C.AND rd', rs2' | CA | Compressed AND |
| 01 | C.ANDI | C.ANDI rd', imm | CB | Compressed AND Immediate |
| 01 | C.BEQZ | C.BEQZ rs1', offset | CB | Compressed Branch if Equal to Zero |
| 01 | C.BNEZ | C.BNEZ rs1', offset | CB | Compressed Branch if Not Equal to Zero |
| 0x9002 | C.EBREAK | C.EBREAK | CR | Compressed Environment Break |
| 00 | C.FLD | C.FLD rd', offset(rs1') | CL | Compressed Float Load Double |
| 02 | C.FLDSP | C.FLDSP rd, offset(x2) | CI | Compressed Float Load Double from Stack Pointer |
| 00 | C.FLW | C.FLW rd', offset(rs1') | CL | Compressed Float Load Word |
| 02 | C.FLWSP | C.FLWSP rd, offset(x2) | CI | Compressed Float Load Word from Stack Pointer |
| 00 | C.FSD | C.FSD rs2', offset(rs1') | CS | Compressed Float Store Double |
| 02 | C.FSDSP | C.FSDSP rs2, offset(x2) | CSS | Compressed Float Store Double to Stack Pointer |
| 00 | C.FSW | C.FSW rs2', offset(rs1') | CS | Compressed Float Store Word |
| 02 | C.FSWSP | C.FSWSP rs2, offset(x2) | CSS | Compressed Float Store Word to Stack Pointer |
| 01 | C.J | C.J offset | CJ | Compressed Jump |
| 01 | C.JAL | C.JAL offset | CJ | Compressed Jump and Link |
| 02 | C.JALR | C.JALR rs1 | CR | Compressed Jump and Link Register |
| 02 | C.JR | C.JR rs1 | CR | Compressed Jump Register |
| 00 | C.LD | C.LD rd', offset(rs1') | CL | Compressed Load Doubleword |
| 02 | C.LDSP | C.LDSP rd, offset(x2) | CI | Compressed Load Doubleword from Stack Pointer |
| 01 | C.LI | C.LI rd, imm | CI | Compressed Load Immediate |
| 01 | C.LUI | C.LUI rd, imm | CI | Compressed Load Upper Immediate |
| 00 | C.LW | C.LW rd', offset(rs1') | CL | Compressed Load Word |
| 02 | C.LWSP | C.LWSP rd, offset(x2) | CI | Compressed Load Word from Stack Pointer |
| 01 | C.MUL | C.MUL rd', rs2' | CA | Compressed Multiply |
| 02 | C.MV | C.MV rd, rs2 | CR | Compressed Move |
| 0x0001 | C.NOP | C.NOP | CI | Compressed No Operation |
| 01 | C.NOT | C.NOT rd' | CR | Compressed Bitwise NOT |
| 01 | C.OR | C.OR rd', rs2' | CA | Compressed OR |
| 00 | C.SD | C.SD rs2', offset(rs1') | CS | Compressed Store Doubleword |
| 02 | C.SDSP | C.SDSP rs2, offset(x2) | CSS | Compressed Store Doubleword to Stack Pointer |
| 01 | C.SEXT.B | C.SEXT.B rd' | CR | Compressed Sign Extend Byte |
| 02 | C.SLLI | C.SLLI rd, imm | CI | Compressed Shift Left Logical Immediate |
| 01 | C.SRAI | C.SRAI rd', imm | CB | Compressed Shift Right Arithmetic Immediate |
| 01 | C.SRLI | C.SRLI rd', imm | CB | Compressed Shift Right Logical Immediate |
| 01 | C.SUB | C.SUB rd', rs2' | CA | Compressed Subtract |
| 01 | C.SUBW | C.SUBW rd', rs2' | CA | Compressed Subtract Word |
| 00 | C.SW | C.SW rs2', offset(rs1') | CS | Compressed Store Word |
| 02 | C.SWSP | C.SWSP rs2, offset(x2) | CSS | Compressed Store Word to Stack Pointer |
| 01 | C.XOR | C.XOR rd', rs2' | CA | Compressed XOR |
| 01 | C.ZEXT.B | C.ZEXT.B rd' | CR | Compressed Zero Extend Byte |
| Variable | CALL | CALL symbol | Pseudo | Call Subroutine |
| 0x0F | CBO.CLEAN | CBO.CLEAN (rs1) | I-Type | Cache Block Operation: Clean |
| 0x0F | CBO.FLUSH | CBO.FLUSH (rs1) | I-Type | Cache Block Operation: Flush |
| 0x0F | CBO.INVAL | CBO.INVAL (rs1) | I-Type | Cache Block Operation: Invalidate |
| 0x0F | CBO.ZERO | CBO.ZERO (rs1) | I-Type | Cache Block Zero |
| 0x33 | CLMUL | CLMUL rd, rs1, rs2 | R-Type | Carry-less Multiply |
| 0x13 | CLZ | CLZ rd, rs1 | I-Type | Count Leading Zeros |
| 0x02 | CM.POP | CM.POP {reg_list}, stack_adj | Push/Pop | Pop Registers |
| 0x02 | CM.PUSH | CM.PUSH {reg_list}, -stack_adj | Push/Pop | Push Registers |
| 0x13 | CPOP | CPOP rd, rs1 | I-Type | Population Count |
| 0x73 | CSRC | CSRC csr, rs | I-Type | Control Status Register Clear |
| 0x73 | CSRR | CSRR rd, csr | I-Type | Control Status Register Read |
| 0x73 | CSRRC | CSRRC rd, csr, rs1 | I-Type | Control Status Register Read and Clear |
| 0x73 | CSRRCI | CSRRCI rd, csr, uimm | I-Type | CSR Read and Clear Immediate |
| 0x73 | CSRRS | CSRRS rd, csr, rs1 | I-Type | Control Status Register Read and Set |
| 0x73 | CSRRSI | CSRRSI rd, csr, uimm | I-Type | CSR Read and Set Immediate |
| 0x73 | CSRRW | CSRRW rd, csr, rs1 | I-Type | Control Status Register Read/Write |
| 0x73 | CSRRWI | CSRRWI rd, csr, uimm | I-Type | CSR Read/Write Immediate |
| 0x73 | CSRS | CSRS csr, rs | I-Type | Control Status Register Set |
| 0x73 | CSRW | CSRW csr, rs | I-Type | Control Status Register Write |
| 0x13 | CTZ | CTZ rd, rs1 | I-Type | Count Trailing Zeros |
| 0x33 | CZERO.EQZ | CZERO.EQZ rd, rs1, rs2 | R-Type | Conditional Zero Equal to Zero |
| 0x33 | CZERO.NEZ | CZERO.NEZ rd, rs1, rs2 | R-Type | Conditional Zero Not Equal to Zero |
| 0x33 | DIV | DIV rd, rs1, rs2 | R-Type | Divide |
| 0x33 | DIVU | DIVU rd, rs1, rs2 | R-Type | Divide Unsigned |
| 0x3B | DIVUW | DIVUW rd, rs1, rs2 | R-Type | Divide Unsigned Word |
| 0x3B | DIVW | DIVW rd, rs1, rs2 | R-Type | Divide Word |
| 0x73 | DRET | DRET | R-Type (System) | Debug Return |
| 0x73 | EBREAK | EBREAK | I-Type | Environment Break |
| 0x73 | ECALL | ECALL | I-Type | Environment Call |
| 0x53 | FADD.D | FADD.D rd, rs1, rs2 | R-Type | Float Add Double |
| 0x53 | FADD.H | FADD.H rd, rs1, rs2 | R-Type | Float Add Half |
| 0x53 | FADD.S | FADD.S rd, rs1, rs2 | R-Type | Float Add (Single) |
| 0x53 | FCLASS.D | FCLASS.D rd, rs1 | R-Type | Float Classify (Double) |
| 0x53 | FCLASS.H | FCLASS.H rd, rs1 | R-Type | Float Classify (Half) |
| 0x53 | FCLASS.S | FCLASS.S rd, rs1 | R-Type | Float Classify (Single) |
| 0x53 | FCVT.D.L | FCVT.D.L rd, rs1 | I-Type (Float) | Convert Long to Double |
| 0x53 | FCVT.D.LU | FCVT.D.LU rd, rs1 | I-Type (Float) | Convert Unsigned Long to Double |
| 0x53 | FCVT.D.S | FCVT.D.S rd, rs1 | I-Type (Float) | Float Convert Single to Double |
| 0x53 | FCVT.D.W | FCVT.D.W rd, rs1 | I-Type (Float) | Convert Word to Double |
| 0x53 | FCVT.D.WU | FCVT.D.WU rd, rs1 | I-Type (Float) | Convert Unsigned Word to Double |
| 0x53 | FCVT.H.S | FCVT.H.S rd, rs1 | I-Type (Float) | Convert Single to Half |
| 0x53 | FCVT.H.W | FCVT.H.W rd, rs1 | I-Type (Float) | Convert Word to Half |
| 0x53 | FCVT.H.WU | FCVT.H.WU rd, rs1 | I-Type (Float) | Convert Unsigned Word to Half |
| 0x53 | FCVT.L.D | FCVT.L.D rd, rs1 | I-Type (Float) | Convert Double to Long |
| 0x53 | FCVT.L.S | FCVT.L.S rd, rs1 | I-Type (Float) | Convert Float to Long |
| 0x53 | FCVT.LU.D | FCVT.LU.D rd, rs1 | I-Type (Float) | Convert Double to Unsigned Long |
| 0x53 | FCVT.LU.S | FCVT.LU.S rd, rs1 | I-Type (Float) | Convert Float to Unsigned Long |
| 0x53 | FCVT.S.D | FCVT.S.D rd, rs1 | I-Type (Float) | Float Convert Double to Single |
| 0x53 | FCVT.S.H | FCVT.S.H rd, rs1 | I-Type (Float) | Convert Half to Single |
| 0x53 | FCVT.S.L | FCVT.S.L rd, rs1 | I-Type (Float) | Convert Long to Float |
| 0x53 | FCVT.S.LU | FCVT.S.LU rd, rs1 | I-Type (Float) | Convert Unsigned Long to Float |
| 0x53 | FCVT.S.W | FCVT.S.W rd, rs1 | I-Type (Float) | Float Convert from Word (Single) |
| 0x53 | FCVT.S.WU | FCVT.S.WU rd, rs1 | I-Type (Float) | Convert Unsigned Word to Float |
| 0x53 | FCVT.W.D | FCVT.W.D rd, rs1 | I-Type (Float) | Convert Double to Word |
| 0x53 | FCVT.W.H | FCVT.W.H rd, rs1 | I-Type (Float) | Convert Half to Word |
| 0x53 | FCVT.W.S | FCVT.W.S rd, rs1 | I-Type (Float) | Float Convert to Word (Single) |
| 0x53 | FCVT.WU.D | FCVT.WU.D rd, rs1 | I-Type (Float) | Convert Double to Unsigned Word |
| 0x53 | FCVT.WU.H | FCVT.WU.H rd, rs1 | I-Type (Float) | Convert Half to Unsigned Word |
| 0x53 | FCVT.WU.S | FCVT.WU.S rd, rs1 | I-Type (Float) | Convert Float to Unsigned Word |
| 0x53 | FDIV.D | FDIV.D rd, rs1, rs2 | R-Type | Float Divide Double |
| 0x53 | FDIV.H | FDIV.H rd, rs1, rs2 | R-Type | Float Divide (Half) |
| 0x53 | FDIV.S | FDIV.S rd, rs1, rs2 | R-Type | Float Divide (Single) |
| 0x0F | FENCE | FENCE pred, succ | I-Type | Fence |
| 0x0F | FENCE.I | FENCE.I | I-Type | Instruction Fence |
| 0x53 | FEQ.D | FEQ.D rd, rs1, rs2 | R-Type | Float Equal (Double) |
| 0x53 | FEQ.H | FEQ.H rd, rs1, rs2 | R-Type | Float Equal (Half) |
| 0x53 | FEQ.S | FEQ.S rd, rs1, rs2 | R-Type | Float Equal (Single) |
| 0x07 | FLD | FLD rd, offset(rs1) | I-Type | Float Load Double |
| 0x53 | FLE.D | FLE.D rd, rs1, rs2 | R-Type | Float Less or Equal (Double) |
| 0x53 | FLE.H | FLE.H rd, rs1, rs2 | R-Type | Float Less or Equal (Half) |
| 0x53 | FLE.S | FLE.S rd, rs1, rs2 | R-Type | Float Less or Equal (Single) |
| 0x07 | FLH | FLH rd, offset(rs1) | I-Type | Float Load Halfword |
| 0x53 | FLI.D | FLI.D rd, rs1 | R-Type | Float Load Immediate (Double) |
| 0x53 | FLI.H | FLI.H rd, rs1 | R-Type | Float Load Immediate (Half) |
| 0x53 | FLI.S | FLI.S rd, rs1 | R-Type | Float Load Immediate (Single) |
| 0x53 | FLT.D | FLT.D rd, rs1, rs2 | R-Type | Float Less Than (Double) |
| 0x53 | FLT.H | FLT.H rd, rs1, rs2 | R-Type | Float Less Than (Half) |
| 0x53 | FLT.S | FLT.S rd, rs1, rs2 | R-Type | Float Less Than (Single) |
| 0x07 | FLW | FLW rd, offset(rs1) | I-Type | Float Load Word |
| 0x43 | FMADD.D | FMADD.D rd, rs1, rs2, rs3 | R4-Type | Float Fused Multiply-Add (Double) |
| 0x43 | FMADD.H | FMADD.H rd, rs1, rs2, rs3 | R4-Type | Float Fused Multiply-Add (Half) |
| 0x43 | FMADD.S | FMADD.S rd, rs1, rs2, rs3 | R4-Type | Float Fused Multiply-Add (Single) |
| 0x53 | FMAX.D | FMAX.D rd, rs1, rs2 | R-Type | Float Maximum (Double) |
| 0x53 | FMAX.H | FMAX.H rd, rs1, rs2 | R-Type | Float Maximum (Half) |
| 0x53 | FMAX.S | FMAX.S rd, rs1, rs2 | R-Type | Float Maximum (Single) |
| 0x53 | FMAXM.S | FMAXM.S rd, rs1, rs2 | R-Type | Float Maximum (IEEE 754-2019) |
| 0x53 | FMIN.D | FMIN.D rd, rs1, rs2 | R-Type | Float Minimum (Double) |
| 0x53 | FMIN.H | FMIN.H rd, rs1, rs2 | R-Type | Float Minimum (Half) |
| 0x53 | FMIN.S | FMIN.S rd, rs1, rs2 | R-Type | Float Minimum (Single) |
| 0x53 | FMINM.S | FMINM.S rd, rs1, rs2 | R-Type | Float Minimum (IEEE 754-2019) |
| 0x47 | FMSUB.D | FMSUB.D rd, rs1, rs2, rs3 | R4-Type | Float Fused Multiply-Subtract (Double) |
| 0x47 | FMSUB.H | FMSUB.H rd, rs1, rs2, rs3 | R4-Type | Float Fused Multiply-Subtract (Half) |
| 0x47 | FMSUB.S | FMSUB.S rd, rs1, rs2, rs3 | R4-Type | Float Fused Multiply-Subtract (Single) |
| 0x53 | FMUL.D | FMUL.D rd, rs1, rs2 | R-Type | Float Multiply Double |
| 0x53 | FMUL.H | FMUL.H rd, rs1, rs2 | R-Type | Float Multiply (Half) |
| 0x53 | FMUL.S | FMUL.S rd, rs1, rs2 | R-Type | Float Multiply (Single) |
| 0x53 | FMV.D.X | FMV.D.X rd, rs1 | I-Type (Float) | Move Integer to Double |
| 0x53 | FMV.W.X | FMV.W.X rd, rs1 | I-Type (Float) | Move Integer to Float |
| 0x53 | FMV.X.D | FMV.X.D rd, rs1 | I-Type (Float) | Move Double to Integer |
| 0x53 | FMV.X.W | FMV.X.W rd, rs1 | I-Type (Float) | Move Float to Integer |
| 0x4F | FNMADD.D | FNMADD.D rd, rs1, rs2, rs3 | R4-Type | Float Negated Fused Multiply-Add (Double) |
| 0x4F | FNMADD.H | FNMADD.H rd, rs1, rs2, rs3 | R4-Type | Float Negated Fused Multiply-Add (Half) |
| 0x4F | FNMADD.S | FNMADD.S rd, rs1, rs2, rs3 | R4-Type | Float Negated Fused Multiply-Add (Single) |
| 0x4B | FNMSUB.D | FNMSUB.D rd, rs1, rs2, rs3 | R4-Type | Float Negated Fused Multiply-Subtract (Double) |
| 0x4B | FNMSUB.H | FNMSUB.H rd, rs1, rs2, rs3 | R4-Type | Float Negated Fused Multiply-Subtract (Half) |
| 0x4B | FNMSUB.S | FNMSUB.S rd, rs1, rs2, rs3 | R4-Type | Float Negated Fused Multiply-Subtract (Single) |
| 0x53 | FROUND.S | FROUND.S rd, rs1, rm | I-Type | Float Round to Integer |
| 0x27 | FSD | FSD rs2, offset(rs1) | S-Type | Float Store Double |
| 0x53 | FSGNJ.D | FSGNJ.D rd, rs1, rs2 | R-Type | Float Sign Injection (Double) |
| 0x53 | FSGNJ.H | FSGNJ.H rd, rs1, rs2 | R-Type | Float Sign Injection (Half) |
| 0x53 | FSGNJ.S | FSGNJ.S rd, rs1, rs2 | R-Type | Float Sign Injection (Single) |
| 0x53 | FSGNJN.D | FSGNJN.D rd, rs1, rs2 | R-Type | Float Sign Injection Negate (Double) |
| 0x53 | FSGNJN.H | FSGNJN.H rd, rs1, rs2 | R-Type | Float Sign Injection Negate (Half) |
| 0x53 | FSGNJN.S | FSGNJN.S rd, rs1, rs2 | R-Type | Float Sign Injection Negate (Single) |
| 0x53 | FSGNJX.D | FSGNJX.D rd, rs1, rs2 | R-Type | Float Sign Injection XOR (Double) |
| 0x53 | FSGNJX.H | FSGNJX.H rd, rs1, rs2 | R-Type | Float Sign Injection XOR (Half) |
| 0x53 | FSGNJX.S | FSGNJX.S rd, rs1, rs2 | R-Type | Float Sign Injection XOR (Single) |
| 0x27 | FSH | FSH rs2, offset(rs1) | S-Type | Float Store Halfword |
| 0x53 | FSQRT.D | FSQRT.D rd, rs1 | I-Type (Float) | Float Square Root (Double) |
| 0x53 | FSQRT.H | FSQRT.H rd, rs1 | I-Type (Float) | Float Square Root (Half) |
| 0x53 | FSQRT.S | FSQRT.S rd, rs1 | I-Type (Float) | Float Square Root (Single) |
| 0x53 | FSUB.D | FSUB.D rd, rs1, rs2 | R-Type | Float Subtract Double |
| 0x53 | FSUB.H | FSUB.H rd, rs1, rs2 | R-Type | Float Subtract (Half) |
| 0x53 | FSUB.S | FSUB.S rd, rs1, rs2 | R-Type | Float Subtract (Single) |
| 0x27 | FSW | FSW rs2, offset(rs1) | S-Type | Float Store Word |
| 0x73 | HFENCE.GVMA | HFENCE.GVMA rs1, rs2 | R-Type | Hypervisor Fence Guest Virtual Memory Address |
| 0x73 | HFENCE.VVMA | HFENCE.VVMA rs1, rs2 | R-Type | Hypervisor Fence Virtual Virtual Memory Address |
| 0x73 | HLV.B | HLV.B rd, (rs1) | R-Type (System) | Hypervisor Load Byte |
| 0x73 | HLV.D | HLV.D rd, (rs1) | R-Type (System) | Hypervisor Load Double |
| 0x73 | HLV.W | HLV.W rd, (rs1) | R-Type (System) | Hypervisor Load Word |
| 0x73 | HLV.WU | HLV.WU rd, (rs1) | R-Type (System) | Hypervisor Load Word Unsigned |
| 0x73 | HSV.B | HSV.B rs2, (rs1) | R-Type (System) | Hypervisor Store Byte |
| 0x73 | HSV.D | HSV.D rs2, (rs1) | R-Type (System) | Hypervisor Store Double |
| 0x73 | HSV.W | HSV.W rs2, (rs1) | R-Type (System) | Hypervisor Store Word |
| 0x6F | J | J offset | J-Type | Jump |
| 0x6F | JAL | JAL rd, offset | J-Type | Jump and Link |
| 0x67 | JALR | JALR rd, offset(rs1) | I-Type | Jump and Link Register |
| 0x67 | JR | JR rs | I-Type | Jump Register |
| 0x03 | LB | LB rd, offset(rs1) | I-Type | Load Byte |
| 0x03 | LBU | LBU rd, offset(rs1) | I-Type | Load Byte Unsigned |
| 0x03 | LD | LD rd, offset(rs1) | I-Type | Load Doubleword |
| 0x03 | LH | LH rd, offset(rs1) | I-Type | Load Halfword |
| 0x03 | LHU | LHU rd, offset(rs1) | I-Type | Load Halfword Unsigned |
| 0x37 | LI | LI rd, imm | U-Type | Load Immediate |
| 0x2F | LR.D | LR.D rd, (rs1) | R-Type (Atomic) | Load Reserved Doubleword |
| 0x2F | LR.W | LR.W rd, (rs1) | R-Type (Atomic) | Load Reserved Word |
| 0x37 | LUI | LUI rd, imm | U-Type | Load Upper Immediate |
| 0x03 | LW | LW rd, offset(rs1) | I-Type | Load Word |
| 0x03 | LWU | LWU rd, offset(rs1) | I-Type | Load Word Unsigned |
| 0x33 | MAX | MAX rd, rs1, rs2 | R-Type | Maximum |
| 0x33 | MAXU | MAXU rd, rs1, rs2 | R-Type | Maximum Unsigned |
| 0x33 | MIN | MIN rd, rs1, rs2 | R-Type | Minimum |
| 0x33 | MINU | MINU rd, rs1, rs2 | R-Type | Minimum Unsigned |
| 0x73 | MRET | MRET | R-Type (System) | Machine Return |
| 0x33 | MUL | MUL rd, rs1, rs2 | R-Type | Multiply |
| 0x33 | MULH | MULH rd, rs1, rs2 | R-Type | Multiply High Signed |
| 0x33 | MULHSU | MULHSU rd, rs1, rs2 | R-Type | Multiply High Signed-Unsigned |
| 0x33 | MULHU | MULHU rd, rs1, rs2 | R-Type | Multiply High Unsigned |
| 0x3B | MULW | MULW rd, rs1, rs2 | R-Type | Multiply Word |
| 0x13 | MV | MV rd, rs | I-Type | Move |
| 0x33 | NEG | NEG rd, rs | R-Type | Negate |
| 0x13 | NOP | NOP | I-Type | No Operation |
| 0x13 | NOT | NOT rd, rs | I-Type | Bitwise NOT |
| 0x33 | NTL.ALL | NTL.ALL | R-Type | Non-Temporal Locality Hint (Store All) |
| 0x33 | NTL.P1 | NTL.P1 | R-Type | Non-Temporal Locality Hint (Prefetch Level 1) |
| 0x33 | NTL.PALL | NTL.PALL | R-Type | Non-Temporal Locality Hint (All Levels) |
| 0x33 | NTL.S1 | NTL.S1 | R-Type | Non-Temporal Locality Hint (Store Level 1) |
| 0x33 | OR | OR rd, rs1, rs2 | R-Type | Logical OR |
| 0x13 | ORC.B | ORC.B rd, rs1 | I-Type | Bitwise OR-Combine Byte |
| 0x13 | ORI | ORI rd, rs1, imm | I-Type | Logical OR Immediate |
| 0x33 | ORN | ORN rd, rs1, rs2 | R-Type | OR Not |
| 0x33 | PACK | PACK rd, rs1, rs2 | R-Type | Pack two words into a register |
| 0x33 | PACKH | PACKH rd, rs1, rs2 | R-Type | Pack Byte |
| 0x0F | PAUSE | PAUSE | I-Type (Hint) | Pause |
| 0x13 | PREFETCH.I | PREFETCH.I offset(rs1) | S-Type (Hint) | Prefetch Instruction |
| 0x13 | PREFETCH.R | PREFETCH.R offset(rs1) | S-Type (Hint) | Prefetch Read |
| 0x13 | PREFETCH.W | PREFETCH.W offset(rs1) | S-Type (Hint) | Prefetch Write |
| 0x73 | RDCYCLE | RDCYCLE rd | I-Type | Read Cycle Counter |
| 0x73 | RDINSTRET | RDINSTRET rd | I-Type | Read Instructions Retired |
| 0x73 | RDTIME | RDTIME rd | I-Type | Read Real-Time Clock |
| 0x33 | REM | REM rd, rs1, rs2 | R-Type | Remainder |
| 0x33 | REMU | REMU rd, rs1, rs2 | R-Type | Remainder Unsigned |
| 0x3B | REMUW | REMUW rd, rs1, rs2 | R-Type | Remainder Unsigned Word |
| 0x3B | REMW | REMW rd, rs1, rs2 | R-Type | Remainder Word |
| 0x67 | RET | RET | I-Type | Return |
| 0x13 | REV8 | REV8 rd, rs1 | I-Type | Byte Reverse |
| 0x33 | ROL | ROL rd, rs1, rs2 | R-Type | Rotate Left |
| 0x33 | ROR | ROR rd, rs1, rs2 | R-Type | Rotate Right |
| 0x23 | SB | SB rs2, offset(rs1) | S-Type | Store Byte |
| 0x2F | SC.D | SC.D rd, rs2, (rs1) | R-Type (Atomic) | Store Conditional Doubleword |
| 0x2F | SC.W | SC.W rd, rs2, (rs1) | R-Type (Atomic) | Store Conditional Word |
| 0x23 | SD | SD rs2, offset(rs1) | S-Type | Store Doubleword |
| 0x13 | SEQZ | SEQZ rd, rs | I-Type | Set if Equal to Zero |
| 0x13 | SEX.B | SEX.B rd, rs1 | I-Type | Sign Extend Byte |
| 0x13 | SEX.H | SEX.H rd, rs1 | I-Type | Sign Extend Halfword |
| 0x73 | SFENCE.INVAL.IR | SFENCE.INVAL.IR | R-Type (System) | Supervisor Fence Invalidate Range |
| 0x73 | SFENCE.VMA | SFENCE.VMA rs1, rs2 | R-Type (System) | Supervisor Fence Virtual Memory |
| 0x73 | SFENCE.W.INVAL | SFENCE.W.INVAL | R-Type (System) | Supervisor Fence Write Invalidate |
| 0x23 | SH | SH rs2, offset(rs1) | S-Type | Store Halfword |
| 0x33 | SH1ADD | SH1ADD rd, rs1, rs2 | R-Type | Shift Left 1 and Add |
| 0x33 | SH2ADD | SH2ADD rd, rs1, rs2 | R-Type | Shift Left 2 and Add |
| 0x33 | SH3ADD | SH3ADD rd, rs1, rs2 | R-Type | Shift Left 3 and Add |
| 0x13 | SHA256SIG0 | SHA256SIG0 rd, rs1 | I-Type | SHA-256 Sigma0 |
| 0x13 | SHA256SUM0 | SHA256SUM0 rd, rs1 | I-Type | SHA-256 Sum0 |
| 0x13 | SHA512SIG0 | SHA512SIG0 rd, rs1 | R-Type | SHA-512 Sigma0 |
| 0x13 | SHA512SIG1 | SHA512SIG1 rd, rs1 | R-Type | SHA-512 Sigma1 |
| 0x13 | SHA512SUM0 | SHA512SUM0 rd, rs1 | R-Type | SHA-512 Sum0 |
| 0x13 | SHA512SUM1 | SHA512SUM1 rd, rs1 | R-Type | SHA-512 Sum1 |
| 0x33 | SLL | SLL rd, rs1, rs2 | R-Type | Shift Left Logical |
| 0x13 | SLLI | SLLI rd, rs1, shamt | I-Type (Shift) | Shift Left Logical Immediate |
| 0x1B | SLLIW | SLLIW rd, rs1, shamt | I-Type (Shift) | Shift Left Logical Immediate Word |
| 0x3B | SLLW | SLLW rd, rs1, rs2 | R-Type | Shift Left Logical Word |
| 0x33 | SLT | SLT rd, rs1, rs2 | R-Type | Set Less Than |
| 0x13 | SLTI | SLTI rd, rs1, imm | I-Type | Set Less Than Immediate |
| 0x13 | SLTIU | SLTIU rd, rs1, imm | I-Type | Set Less Than Immediate Unsigned |
| 0x33 | SLTU | SLTU rd, rs1, rs2 | R-Type | Set Less Than Unsigned |
| 0x13 | SM3P0 | SM3P0 rd, rs1 | R-Type | SM3 P0 Transformation |
| 0x13 | SM3P1 | SM3P1 rd, rs1 | R-Type | SM3 P1 Transformation |
| 0x33 | SM4ED | SM4ED rd, rs1, rs2, bs | R-Type | SM4 Encryption/Decryption |
| 0x33 | SM4KS | SM4KS rd, rs1, rs2, bs | R-Type | SM4 Key Schedule |
| 0x33 | SNEZ | SNEZ rd, rs | R-Type | Set if Not Equal to Zero |
| 0x33 | SRA | SRA rd, rs1, rs2 | R-Type | Shift Right Arithmetic |
| 0x1B | SRAIW | SRAIW rd, rs1, shamt | I-Type (Shift) | Shift Right Arithmetic Immediate Word |
| 0x3B | SRAW | SRAW rd, rs1, rs2 | R-Type | Shift Right Arithmetic Word |
| 0x73 | SRET | SRET | R-Type (System) | Supervisor Return |
| 0x33 | SRL | SRL rd, rs1, rs2 | R-Type | Shift Right Logical |
| 0x1B | SRLIW | SRLIW rd, rs1, shamt | I-Type (Shift) | Shift Right Logical Immediate Word |
| 0x3B | SRLW | SRLW rd, rs1, rs2 | R-Type | Shift Right Logical Word |
| 0x33 | SUB | SUB rd, rs1, rs2 | R-Type | Subtract |
| 0x3B | SUBW | SUBW rd, rs1, rs2 | R-Type | Subtract Word |
| 0x23 | SW | SW rs2, offset(rs1) | S-Type | Store Word |
| 0x73 | URET | URET | R-Type (System) | User Return |
| 0x57 | VAADD.VV | VAADD.VV vd, vs2, vs1, vm | OPIVV | Vector Averaging Add |
| 0x57 | VAADDU.VV | VAADDU.VV vd, vs2, vs1, vm | OPIVV | Vector Averaging Add Unsigned |
| 0x57 | VADC.VVM | VADC.VVM vd, vs2, vs1, v0 | OPIVV | Vector Add with Carry |
| 0x57 | VADD.VI | VADD.VI vd, vs2, imm, vm | OPIVI | Vector Add Immediate |
| 0x57 | VADD.VV | VADD.VV vd, vs2, vs1, vm | OPIVV | Vector Integer Add |
| 0x57 | VADDC.VVM | VADDC.VVM vd, vs2, vs1, v0 | OPIVV | Vector Add with Carry |
| 0x57 | VAESDF.VV | VAESDF.VV vd, vs2, vs1 | OPIVV | Vector AES Decryption Final Round |
| 0x57 | VAESDM.VV | VAESDM.VV vd, vs2, vs1 | OPIVV | Vector AES Decryption Middle Round |
| 0x57 | VAESEF.VV | VAESEF.VV vd, vs2, vs1 | OPIVV | Vector AES Encryption Final Round |
| 0x57 | VAESEM.VV | VAESEM.VV vd, vs2, vs1 | OPIVV | Vector AES Encryption Middle Round |
| 0x57 | VAESKF1.VI | VAESKF1.VI vd, vs2, uimm | OPIVI | Vector AES Key Expansion 1 |
| 0x57 | VAESKF2.VI | VAESKF2.VI vd, vs2, uimm | OPIVI | Vector AES Key Expansion 2 |
| 0x2F | VAMOADDD.V | VAMOADDD.V vd, (rs1), vs2, vm | VAMO | Vector Atomic Add Doubleword |
| 0x2F | VAMOADDW.V | VAMOADDW.V vd, (rs1), vs2, vm | VAMO | Vector Atomic Add Word |
| 0x2F | VAMOANDD.V | VAMOANDD.V vd, (rs1), vs2, vm | VAMO | Vector Atomic AND Doubleword |
| 0x2F | VAMOANDW.V | VAMOANDW.V vd, (rs1), vs2, vm | VAMO | Vector Atomic AND Word |
| 0x2F | VAMOMAXD.V | VAMOMAXD.V vd, (rs1), vs2, vm | VAMO | Vector Atomic Max Doubleword |
| 0x2F | VAMOMAXU.V | VAMOMAXU.V vd, (rs1), vs2, vm | VAMO | Vector Atomic Max Unsigned |
| 0x2F | VAMOMAXW.V | VAMOMAXW.V vd, (rs1), vs2, vm | VAMO | Vector Atomic Max Word |
| 0x2F | VAMOMIND.V | VAMOMIND.V vd, (rs1), vs2, vm | VAMO | Vector Atomic Min Doubleword |
| 0x2F | VAMOMINU.V | VAMOMINU.V vd, (rs1), vs2, vm | VAMO | Vector Atomic Min Unsigned |
| 0x2F | VAMOMINW.V | VAMOMINW.V vd, (rs1), vs2, vm | VAMO | Vector Atomic Min Word |
| 0x2F | VAMOORD.V | VAMOORD.V vd, (rs1), vs2, vm | VAMO | Vector Atomic OR Doubleword |
| 0x2F | VAMOORW.V | VAMOORW.V vd, (rs1), vs2, vm | VAMO | Vector Atomic OR Word |
| 0x2F | VAMOXORD.V | VAMOXORD.V vd, (rs1), vs2, vm | VAMO | Vector Atomic XOR Doubleword |
| 0x2F | VAMOXORW.V | VAMOXORW.V vd, (rs1), vs2, vm | VAMO | Vector Atomic XOR Word |
| 0x57 | VAND.VI | VAND.VI vd, vs2, imm, vm | OPIVI | Vector AND Immediate |
| 0x57 | VANDN.VV | VANDN.VV vd, vs2, vs1, vm | OPIVV | Vector Bitwise AND-NOT |
| 0x57 | VANDN.VX | VANDN.VX vd, vs2, rs1, vm | OPIVX | Vector Bitwise AND-NOT Scalar |
| 0x57 | VASUB.VV | VASUB.VV vd, vs2, vs1, vm | OPIVV | Vector Averaging Subtract Signed |
| 0x57 | VASUBU.VV | VASUBU.VV vd, vs2, vs1, vm | OPIVV | Vector Averaging Subtract Unsigned |
| 0x57 | VBREV8.V | VBREV8.V vd, vs2, vm | OPIVV | Vector Byte Reverse |
| 0x57 | VCLMUL.VV | VCLMUL.VV vd, vs2, vs1, vm | OPIVV | Vector Carry-less Multiply |
| 0x57 | VCLMULH.VV | VCLMULH.VV vd, vs2, vs1, vm | OPIVV | Vector Carry-less Multiply High |
| 0x57 | VCLZ.V | VCLZ.V vd, vs2, vm | OPIVV | Vector Count Leading Zeros |
| 0x57 | VCOMPRESS.VM | VCOMPRESS.VM vd, vs2, vs1 | OPMVV | Vector Compress |
| 0x57 | VCPOP.M | VCPOP.M rd, vs2, vm | OPMVX | Vector Mask Population Count |
| 0x57 | VCPOP.V | VCPOP.V vd, vs2, vm | OPIVV | Vector Population Count |
| 0x57 | VCTZ.V | VCTZ.V vd, vs2, vm | OPIVV | Vector Count Trailing Zeros |
| 0x57 | VDIV.VV | VDIV.VV vd, vs2, vs1, vm | OPIVV | Vector Integer Divide Signed |
| 0x57 | VDIVU.VV | VDIVU.VV vd, vs2, vs1, vm | OPIVV | Vector Integer Divide Unsigned |
| 0x57 | VFADD.VV | VFADD.VV vd, vs2, vs1, vm | OPFVV | Vector Float Add |
| 0x57 | VFCLASS.V | VFCLASS.V vd, vs2, vm | OPFVV | Vector Float Classify |
| 0x57 | VFCVT.F.X.V | VFCVT.F.X.V vd, vs2, vm | OPFVV | Vector Signed Integer to Float Convert |
| 0x57 | VFCVT.X.F.V | VFCVT.X.F.V vd, vs2, vm | OPFVV | Vector Float to Signed Integer Convert |
| 0x57 | VFDIV.VV | VFDIV.VV vd, vs2, vs1, vm | OPFVV | Vector Float Divide |
| 0x57 | VFIRST.M | VFIRST.M rd, vs2, vm | OPMVX | Vector Find First Set Mask Bit |
| 0x57 | VFMADD.VV | VFMADD.VV vd, vs1, vs2, vm | OPFVV | Vector Float Fused Multiply-Add |
| 0x57 | VFMAX.VV | VFMAX.VV vd, vs2, vs1, vm | OPFVV | Vector Float Maximum |
| 0x57 | VFMIN.VV | VFMIN.VV vd, vs2, vs1, vm | OPFVV | Vector Float Minimum |
| 0x57 | VFMUL.VV | VFMUL.VV vd, vs2, vs1, vm | OPFVV | Vector Float Multiply |
| 0x57 | VFMV.F.S | VFMV.F.S fd, vs2 | OPFVW | Vector Move Float to Scalar |
| 0x57 | VFMV.S.F | VFMV.S.F vd, fs1 | OPFVW | Vector Move Scalar to Float |
| 0x57 | VFNCVT.F.F.W | VFNCVT.F.F.W vd, vs2, vm | OPFVV | Vector Narrowing Float Convert |
| 0x57 | VFNCVT.X.F.W | VFNCVT.X.F.W vd, vs2, vm | OPFVV | Vector Narrowing Float to Signed Int |
| 0x57 | VFREC7.V | VFREC7.V vd, vs2, vm | OPFVV | Vector Float Reciprocal Estimate 7-bit |
| 0x57 | VFREDMAX.VS | VFREDMAX.VS vd, vs2, vs1, vm | OPFVV | Vector Float Reduction Maximum |
| 0x57 | VFREDOSUM.VS | VFREDOSUM.VS vd, vs2, vs1, vm | OPFVV | Vector Ordered Float Reduction Sum |
| 0x57 | VFREDUSUM.VS | VFREDUSUM.VS vd, vs2, vs1, vm | OPFVV | Vector Unordered Float Reduction Sum |
| 0x57 | VFRSQRT7.V | VFRSQRT7.V vd, vs2, vm | OPFVV | Vector Float Reciprocal Sqrt Estimate 7-bit |
| 0x57 | VFSGNJ.VV | VFSGNJ.VV vd, vs2, vs1, vm | OPFVV | Vector Float Sign Injection |
| 0x57 | VFSQRT.V | VFSQRT.V vd, vs2, vm | OPFVV | Vector Float Square Root |
| 0x57 | VFWADD.VV | VFWADD.VV vd, vs2, vs1, vm | OPFVV | Vector Widening Float Add |
| 0x57 | VFWCVT.F.F.V | VFWCVT.F.F.V vd, vs2, vm | OPFVV | Vector Widening Float to Float Convert |
| 0x57 | VFWCVT.F.X.V | VFWCVT.F.X.V vd, vs2, vm | OPFVV | Vector Widening Integer to Float Convert |
| 0x57 | VFWCVT.X.F.V | VFWCVT.X.F.V vd, vs2, vm | OPFVV | Vector Widening Float to Signed Int |
| 0x57 | VFWMUL.VV | VFWMUL.VV vd, vs2, vs1, vm | OPFVV | Vector Widening Float Multiply |
| 0x57 | VFWREDOSUM.VS | VFWREDOSUM.VS vd, vs2, vs1, vm | OPFVV | Vector Widening Ordered Float Reduction Sum |
| 0x57 | VFWREDUSUM.VS | VFWREDUSUM.VS vd, vs2, vs1, vm | OPFVV | Vector Widening Unordered Float Reduction Sum |
| 0x57 | VGHSH.VV | VGHSH.VV vd, vs2, vs1 | OPIVV | Vector GCM Hash |
| 0x57 | VGSHA.VV | VGSHA.VV vd, vs2, vs1 | OPIVV | Vector GCM Hash Accumulate |
| 0x57 | VID.V | VID.V vd, vm | OPMVV | Vector Element Index |
| 0x57 | VIOTA.M | VIOTA.M vd, vs2, vm | OPMVV | Vector Iota |
| 0x07 | VLE16.V | VLE16.V vd, (rs1), vm | VL-Type | Vector Load Element (16-bit) |
| 0x07 | VLE16FF.V | VLE16FF.V vd, (rs1), vm | VL-Type | Vector Load 16-bit Fault-Only-First |
| 0x07 | VLE32.V | VLE32.V vd, (rs1), vm | V-Load | Vector Load Element (32-bit) |
| 0x07 | VLE32FF.V | VLE32FF.V vd, (rs1), vm | VL-Type | Vector Load 32-bit Fault-Only-First |
| 0x07 | VLE64.V | VLE64.V vd, (rs1), vm | VL-Type | Vector Load Element (64-bit) |
| 0x07 | VLE64FF.V | VLE64FF.V vd, (rs1), vm | VL-Type | Vector Load 64-bit Fault-Only-First |
| 0x07 | VLE8.V | VLE8.V vd, (rs1), vm | VL-Type | Vector Load Element (8-bit) |
| 0x07 | VLE8FF.V | VLE8FF.V vd, (rs1), vm | VL-Type | Vector Load 8-bit Fault-Only-First |
| 0x07 | VLM.V | VLM.V vd, (rs1) | VL-Type | Vector Load Mask |
| 0x07 | VLOXEI32.V | VLOXEI32.V vd, (rs1), vs2, vm | VL-Type | Vector Load Ordered Indexed (32-bit indices) |
| 0x07 | VLSE32.V | VLSE32.V vd, (rs1), rs2, vm | VL-Type | Vector Load Strided Element (32-bit) |
| 0x07 | VLSEG2E16.V | VLSEG2E16.V vd, (rs1), vm | VL-Type | Vector Load Segment (2 fields, 16-bit) |
| 0x07 | VLSEG3E8.V | VLSEG3E8.V vd, (rs1), vm | VL-Type | Vector Load Segment (3 fields, 8-bit) |
| 0x07 | VLSEG4E8.V | VLSEG4E8.V vd, (rs1), vm | VL-Type | Vector Load Segment (4 fields, 8-bit) |
| 0x07 | VLUXEI32.V | VLUXEI32.V vd, (rs1), vs2, vm | VL-Type | Vector Load Unordered Indexed (32-bit indices) |
| 0x57 | VMACC.VV | VMACC.VV vd, vs1, vs2, vm | OPIVV | Vector Integer Multiply-Accumulate |
| 0x57 | VMADC.VIM | VMADC.VIM vd, vs2, imm, v0 | OPIVI | Vector Mask Add with Carry Immediate |
| 0x57 | VMADC.VVM | VMADC.VVM vd, vs2, vs1, v0 | OPIVV | Vector Add with Carry (Produce Mask) |
| 0x57 | VMAND.MM | VMAND.MM vd, vs2, vs1 | OPMVV | Vector Mask AND |
| 0x57 | VMANDN.MM | VMANDN.MM vd, vs2, vs1 | OPMVV | Vector Mask AND NOT |
| 0x57 | VMAX.VV | VMAX.VV vd, vs2, vs1, vm | OPIVV | Vector Maximum (Signed) |
| 0x57 | VMAXU.VV | VMAXU.VV vd, vs2, vs1, vm | OPIVV | Vector Maximum (Unsigned) |
| 0x57 | VMERGE.VIM | VMERGE.VIM vd, vs2, imm, v0 | OPIVI | Vector Merge Immediate |
| 0x57 | VMERGE.VVM | VMERGE.VVM vd, vs2, vs1, v0 | OPIVV | Vector Merge |
| 0x57 | VMERGE.VXM | VMERGE.VXM vd, vs2, rs1, v0 | OPIVX | Vector Merge Scalar |
| 0x57 | VMFEQ.VV | VMFEQ.VV vd, vs2, vs1, vm | OPFVV | Vector Float Equal |
| 0x57 | VMFLE.VV | VMFLE.VV vd, vs2, vs1, vm | OPFVV | Vector Float Less or Equal |
| 0x57 | VMFLT.VV | VMFLT.VV vd, vs2, vs1, vm | OPFVV | Vector Float Less Than |
| 0x57 | VMIN.VV | VMIN.VV vd, vs2, vs1, vm | OPIVV | Vector Minimum (Signed) |
| 0x57 | VMINU.VV | VMINU.VV vd, vs2, vs1, vm | OPIVV | Vector Minimum (Unsigned) |
| 0x57 | VMNAND.MM | VMNAND.MM vd, vs2, vs1 | OPMVV | Vector Mask NAND |
| 0x57 | VMORN.MM | VMORN.MM vd, vs2, vs1 | OPMVV | Vector Mask OR NOT |
| 0x57 | VMSBC.VV | VMSBC.VV vd, vs2, vs1 | OPMVV | Vector Mask Set Before First |
| 0x57 | VMSBF.M | VMSBF.M vd, vs2, vm | OPMVV | Vector Mask Set Before First |
| 0x57 | VMSEQ.VI | VMSEQ.VI vd, vs2, imm, vm | OPIVI | Vector Mask Set Equal Immediate |
| 0x57 | VMSEQ.VV | VMSEQ.VV vd, vs2, vs1, vm | OPIVV | Vector Mask Set Equal |
| 0x57 | VMSGE.VV | VMSGE.VV vd, vs2, vs1, vm | OPIVV | Vector Mask Set Greater or Equal (Signed) |
| 0x57 | VMSGEU.VV | VMSGEU.VV vd, vs2, vs1, vm | OPIVV | Vector Mask Set Greater or Equal (Unsigned) |
| 0x57 | VMSGT.VV | VMSGT.VV vd, vs2, vs1, vm | OPIVV | Vector Mask Set Greater Than (Signed) |
| 0x57 | VMSGTU.VV | VMSGTU.VV vd, vs2, vs1, vm | OPIVV | Vector Mask Set Greater Than (Unsigned) |
| 0x57 | VMSIF.M | VMSIF.M vd, vs2, vm | OPMVV | Vector Mask Set Including First |
| 0x57 | VMSLE.VI | VMSLE.VI vd, vs2, imm, vm | OPIVI | Vector Mask Set Less or Equal Immediate |
| 0x57 | VMSLE.VV | VMSLE.VV vd, vs2, vs1, vm | OPIVV | Vector Mask Set Less or Equal (Signed) |
| 0x57 | VMSLEU.VI | VMSLEU.VI vd, vs2, imm, vm | OPIVI | Vector Mask Set Less or Equal Unsigned Immediate |
| 0x57 | VMSLEU.VV | VMSLEU.VV vd, vs2, vs1, vm | OPIVV | Vector Mask Set Less or Equal (Unsigned) |
| 0x57 | VMSLT.VI | VMSLT.VI vd, vs2, imm, vm | OPIVI | Vector Mask Set Less Than Immediate |
| 0x57 | VMSLT.VV | VMSLT.VV vd, vs2, vs1, vm | OPIVV | Vector Mask Set Less Than (Signed) |
| 0x57 | VMSLTU.VI | VMSLTU.VI vd, vs2, imm, vm | OPIVI | Vector Mask Set Less Than Unsigned Immediate |
| 0x57 | VMSLTU.VV | VMSLTU.VV vd, vs2, vs1, vm | OPIVV | Vector Mask Set Less Than (Unsigned) |
| 0x57 | VMSNE.VI | VMSNE.VI vd, vs2, imm, vm | OPIVI | Vector Mask Set Not Equal Immediate |
| 0x57 | VMSOF.M | VMSOF.M vd, vs2, vm | OPMVV | Vector Mask Set Only First |
| 0x57 | VMUL.VV | VMUL.VV vd, vs2, vs1, vm | OPIVV | Vector Integer Multiply |
| 0x57 | VMULH.VV | VMULH.VV vd, vs2, vs1, vm | OPIVV | Vector Multiply High Signed |
| 0x57 | VMULHU.VV | VMULHU.VV vd, vs2, vs1, vm | OPIVV | Vector Multiply High Unsigned |
| 0x57 | VMV.S.X | VMV.S.X vd, rs1 | OPMVX | Vector Move Integer to Scalar |
| 0x57 | VMV.V.V | VMV.V.V vd, vs1 | OPIVV | Vector Move |
| 0x57 | VMV.X.S | VMV.X.S rd, vs2 | OPMVX | Vector Move Scalar to Integer |
| 0x57 | VMV1R.V | VMV1R.V vd, vs2 | OPVI | Vector Move 1 Register (Whole) |
| 0x57 | VMV2R.V | VMV2R.V vd, vs2 | OPVI | Vector Move 2 Registers (Whole) |
| 0x57 | VMV4R.V | VMV4R.V vd, vs2 | OPVI | Vector Move 4 Registers (Whole) |
| 0x57 | VMV8R.V | VMV8R.V vd, vs2 | OPVI | Vector Move 8 Registers (Whole) |
| 0x57 | VMXNOR.MM | VMXNOR.MM vd, vs2, vs1 | OPMVV | Vector Mask XNOR |
| 0x57 | VNCLIP.WV | VNCLIP.WV vd, vs2, vs1, vm | OPIVV | Vector Narrowing Clip (Arithmetic Shift) |
| 0x57 | VNCLIPU.WI | VNCLIPU.WI vd, vs2, imm, vm | OPIVI | Vector Narrowing Clip Unsigned (Immediate) |
| 0x57 | VNMSUB.VV | VNMSUB.VV vd, vs1, vs2, vm | OPIVV | Vector Integer Negative Multiply-Subtract |
| 0x57 | VNSRA.WI | VNSRA.WI vd, vs2, imm, vm | OPIVI | Vector Narrowing Shift Right Arithmetic Immediate |
| 0x57 | VNSRA.WX | VNSRA.WX vd, vs2, rs1, vm | OPIVX | Vector Narrowing Shift Right Arithmetic |
| 0x57 | VNSRL.WI | VNSRL.WI vd, vs2, imm, vm | OPIVI | Vector Narrowing Shift Right Logical Immediate |
| 0x57 | VNSRL.WX | VNSRL.WX vd, vs2, rs1, vm | OPIVX | Vector Narrowing Shift Right Logical |
| 0x57 | VOR.VI | VOR.VI vd, vs2, imm, vm | OPIVI | Vector OR Immediate |
| 0x57 | VOR.VV | VOR.VV vd, vs2, vs1, vm | OPIVV | Vector Bitwise OR |
| 0x57 | VORN.VV | VORN.VV vd, vs2, vs1, vm | OPIVV | Vector Bitwise OR-NOT |
| 0x57 | VORN.VX | VORN.VX vd, vs2, rs1, vm | OPIVX | Vector Bitwise OR-NOT Scalar |
| 0x57 | VREDAND.VS | VREDAND.VS vd, vs2, vs1, vm | OPMVV | Vector Reduction AND |
| 0x57 | VREDMAX.VS | VREDMAX.VS vd, vs2, vs1, vm | OPMVV | Vector Reduction Maximum (Signed) |
| 0x57 | VREDMIN.VS | VREDMIN.VS vd, vs2, vs1, vm | OPMVV | Vector Reduction Minimum (Signed) |
| 0x57 | VREDOR.VS | VREDOR.VS vd, vs2, vs1, vm | OPMVV | Vector Reduction OR |
| 0x57 | VREDSUM.VS | VREDSUM.VS vd, vs2, vs1, vm | OPMVV | Vector Reduction Sum |
| 0x57 | VREM.VV | VREM.VV vd, vs2, vs1, vm | OPIVV | Vector Remainder Signed |
| 0x57 | VREMU.VV | VREMU.VV vd, vs2, vs1, vm | OPIVV | Vector Remainder Unsigned |
| 0x57 | VREV8.V | VREV8.V vd, vs2, vm | OPIVV | Vector Reverse 8 |
| 0x57 | VRGATHER.VI | VRGATHER.VI vd, vs2, imm, vm | OPIVI | Vector Register Gather Immediate |
| 0x57 | VRGATHER.VV | VRGATHER.VV vd, vs2, vs1, vm | OPIVV | Vector Register Gather |
| 0x57 | VROL.VV | VROL.VV vd, vs2, vs1, vm | OPIVV | Vector Rotate Left |
| 0x57 | VROL.VX | VROL.VX vd, vs2, rs1, vm | OPIVX | Vector Rotate Left Scalar |
| 0x57 | VROR.VV | VROR.VV vd, vs2, vs1, vm | OPIVV | Vector Rotate Right |
| 0x57 | VROR.VX | VROR.VX vd, vs2, rs1, vm | OPIVX | Vector Rotate Right Scalar |
| 0x57 | VRSUB.VI | VRSUB.VI vd, vs2, imm, vm | OPIVI | Vector Reverse Subtract Immediate |
| 0x57 | VRSUB.VX | VRSUB.VX vd, vs2, rs1, vm | OPIVX | Vector Integer Reverse Subtract Scalar |
| 0x57 | VSADD.VV | VSADD.VV vd, vs2, vs1, vm | OPIVV | Vector Saturating Integer Add |
| 0x57 | VSADDU.VV | VSADDU.VV vd, vs2, vs1, vm | OPIVV | Vector Saturating Integer Add Unsigned |
| 0x57 | VSBC.VVM | VSBC.VVM vd, vs2, vs1, v0 | OPIVV | Vector Subtract with Borrow |
| 0x27 | VSE16.V | VSE16.V vs3, (rs1), vm | VS-Type | Vector Store Element (16-bit) |
| 0x27 | VSE32.V | VSE32.V vs3, (rs1), vm | V-Store | Vector Store Element (32-bit) |
| 0x27 | VSE64.V | VSE64.V vs3, (rs1), vm | VS-Type | Vector Store Element (64-bit) |
| 0x27 | VSE8.V | VSE8.V vs3, (rs1), vm | VS-Type | Vector Store Element (8-bit) |
| 0x57 | VSETIVLI | VSETIVLI rd, uimm, vtypei | V-Type | Vector Set VL Immediate |
| 0x57 | VSETVL | VSETVL rd, rs1, rs2 | V-Type | Vector Set VL |
| 0x57 | VSETVLI | VSETVLI rd, rs1, vtypei | V-Type | Vector Set VL Immediate |
| 0x57 | VSHA2CH.VV | VSHA2CH.VV vd, vs2, vs1 | OPIVV | Vector SHA-2 Compress High |
| 0x57 | VSHA2CL.VV | VSHA2CL.VV vd, vs2, vs1 | OPIVV | Vector SHA-2 Compress Low |
| 0x57 | VSHA2MS.VV | VSHA2MS.VV vd, vs2, vs1 | OPIVV | Vector SHA-2 Message Schedule |
| 0x57 | VSLIDE1DOWN.VX | VSLIDE1DOWN.VX vd, vs2, rs1, vm | OPIVX | Vector Slide One Element Down |
| 0x57 | VSLIDE1UP.VX | VSLIDE1UP.VX vd, vs2, rs1, vm | OPIVX | Vector Slide One Element Up |
| 0x57 | VSLIDEDOWN.VI | VSLIDEDOWN.VI vd, vs2, imm, vm | OPIVI | Vector Slide Down Immediate |
| 0x57 | VSLIDEDOWN.VX | VSLIDEDOWN.VX vd, vs2, rs1, vm | OPIVX | Vector Slide Down |
| 0x57 | VSLIDEUP.VI | VSLIDEUP.VI vd, vs2, imm, vm | OPIVI | Vector Slide Up Immediate |
| 0x57 | VSLIDEUP.VX | VSLIDEUP.VX vd, vs2, rs1, vm | OPIVX | Vector Slide Up |
| 0x57 | VSLL.VI | VSLL.VI vd, vs2, imm, vm | OPIVI | Vector Shift Left Logical Immediate |
| 0x57 | VSLL.VV | VSLL.VV vd, vs2, vs1, vm | OPIVV | Vector Shift Left Logical |
| 0x27 | VSM.V | VSM.V vs3, (rs1) | VS-Type | Vector Store Mask |
| 0x57 | VSMUL.VV | VSMUL.VV vd, vs2, vs1, vm | OPIVV | Vector Single-Width Saturating Multiply |
| 0x27 | VSOXEI32.V | VSOXEI32.V vs3, (rs1), vs2, vm | VS-Type | Vector Store Ordered Indexed (32-bit indices) |
| 0x57 | VSRA.VI | VSRA.VI vd, vs2, imm, vm | OPIVI | Vector Shift Right Arithmetic Immediate |
| 0x57 | VSRA.VV | VSRA.VV vd, vs2, vs1, vm | OPIVV | Vector Shift Right Arithmetic |
| 0x57 | VSRL.VI | VSRL.VI vd, vs2, imm, vm | OPIVI | Vector Shift Right Logical Immediate |
| 0x57 | VSRL.VV | VSRL.VV vd, vs2, vs1, vm | OPIVV | Vector Shift Right Logical |
| 0x27 | VSSE32.V | VSSE32.V vs3, (rs1), rs2, vm | VS-Type | Vector Store Strided Element (32-bit) |
| 0x27 | VSSEG2E16.V | VSSEG2E16.V vs3, (rs1), vm | VS-Type | Vector Store Segment (2 fields, 16-bit) |
| 0x27 | VSSEG3E8.V | VSSEG3E8.V vs3, (rs1), vm | VS-Type | Vector Store Segment (3 fields, 8-bit) |
| 0x27 | VSSEG4E8.V | VSSEG4E8.V vs3, (rs1), vm | VS-Type | Vector Store Segment (4 fields, 8-bit) |
| 0x57 | VSSRA.VV | VSSRA.VV vd, vs2, vs1, vm | OPIVV | Vector Saturating Shift Right Arithmetic |
| 0x57 | VSSRL.VV | VSSRL.VV vd, vs2, vs1, vm | OPIVV | Vector Saturating Shift Right Logical |
| 0x57 | VSSUB.VV | VSSUB.VV vd, vs2, vs1, vm | OPIVV | Vector Saturating Integer Subtract |
| 0x57 | VSSUBU.VV | VSSUBU.VV vd, vs2, vs1, vm | OPIVV | Vector Saturating Integer Subtract Unsigned |
| 0x57 | VSUB.VV | VSUB.VV vd, vs2, vs1, vm | OPIVV | Vector Integer Subtract |
| 0x27 | VSUXEI32.V | VSUXEI32.V vs3, (rs1), vs2, vm | VS-Type | Vector Store Unordered Indexed (32-bit indices) |
| 0x57 | VWADD.VV | VWADD.VV vd, vs2, vs1, vm | OPIVV | Vector Widening Integer Add |
| 0x57 | VWADDU.VV | VWADDU.VV vd, vs2, vs1, vm | OPIVV | Vector Widening Integer Add Unsigned |
| 0x57 | VWMACC.VV | VWMACC.VV vd, vs1, vs2, vm | OPIVV | Vector Widening Multiply-Accumulate |
| 0x57 | VWMACCSU.VV | VWMACCSU.VV vd, vs1, vs2, vm | OPIVV | Vector Widening MAC (Signed * Unsigned) |
| 0x57 | VWMACCU.VV | VWMACCU.VV vd, vs1, vs2, vm | OPIVV | Vector Widening Multiply-Accumulate Unsigned |
| 0x57 | VWMACCUS.VV | VWMACCUS.VV vd, vs1, vs2, vm | OPIVV | Vector Widening MAC (Unsigned * Signed) |
| 0x57 | VWMUL.VV | VWMUL.VV vd, vs2, vs1, vm | OPIVV | Vector Widening Integer Multiply |
| 0x57 | VWREDSUM.VS | VWREDSUM.VS vd, vs2, vs1, vm | OPMVV | Vector Widening Reduction Sum Signed |
| 0x57 | VWREDSUMU.VS | VWREDSUMU.VS vd, vs2, vs1, vm | OPMVV | Vector Widening Reduction Sum Unsigned |
| 0x57 | VWSLL.VI | VWSLL.VI vd, vs2, imm, vm | OPIVI | Vector Widening Shift Left Logical Immediate |
| 0x57 | VWSLL.VV | VWSLL.VV vd, vs2, vs1, vm | OPIVV | Vector Widening Shift Left Logical |
| 0x57 | VWSLL.VX | VWSLL.VX vd, vs2, rs1, vm | OPIVX | Vector Widening Shift Left Logical Scalar |
| 0x57 | VWSUB.VV | VWSUB.VV vd, vs2, vs1, vm | OPIVV | Vector Widening Integer Subtract |
| 0x57 | VXNOR.VV | VXNOR.VV vd, vs2, vs1, vm | OPIVV | Vector Bitwise XNOR |
| 0x57 | VXNOR.VX | VXNOR.VX vd, vs2, rs1, vm | OPIVX | Vector Bitwise XNOR Scalar |
| 0x57 | VXOR.VI | VXOR.VI vd, vs2, imm, vm | OPIVI | Vector XOR Immediate |
| 0x57 | VXOR.VV | VXOR.VV vd, vs2, vs1, vm | OPIVV | Vector Bitwise XOR |
| 0x73 | WFI | WFI | R-Type (System) | Wait for Interrupt |
| 0x73 | WRS.NTO | WRS.NTO | I-Type | Wait on Reservation Set (Normal Time-Out) |
| 0x73 | WRS.STO | WRS.STO | I-Type | Wait on Reservation Set (Short Time-Out) |
| 0x33 | XNOR | XNOR rd, rs1, rs2 | R-Type | Exclusive NOR |
| 0x33 | XOR | XOR rd, rs1, rs2 | R-Type | Logical XOR |
| 0x13 | XORI | XORI rd, rs1, imm | I-Type | Logical XOR Immediate |
| 0x3B | ZEXT.H | ZEXT.H rd, rs1 | I-Type | Zero Extend Halfword |