CSRRSI

CSR Read and Set Immediate

CSRRSI rd, csr, uimm

Sets bits in a CSR using a 5-bit unsigned immediate.

Encoding

Binary Layout

csr

31:20

zimm5

19:15

110

14:12

rd

11:7

1110011

6:0

 

Format I-Type

Opcode 0x00006073

Extension Zicsr

Operands

• rd
  Destination register (integer)
• csr
  CSR Address
• uimm
  Bit Mask

Example

CSRRSI x0, sstatus, 1

// Sets bit 0 of sstatus.

Related

More in Zicsr

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

CSRRSI atomically reads CSR csr into rd, then sets bits in the CSR corresponding to set bits in the zero-extended 5-bit immediate. If the immediate is zero, no bits are modified.

Operation

t = CSRs[csr]; CSRs[csr] = t | zext(uimm); R[rd] = t;