Enable and Disable Interrupts
Mask interrupts around a critical section.
System
Semantics
Clear a bit to stop the processor taking asynchronous interrupts, and set it to resume. The differences are whether there is a dedicated instruction, and how finely the masking can be aimed.
| Architecture | Instructions | Expressed as | How this architecture does it |
|---|---|---|---|
| x86 | one instruction | Two single-purpose instructions on the interrupt flag. STI takes effect one instruction late by design, so that STI followed by HLT cannot lose a wakeup in the gap. | |
| ARM | one instruction | MSR DAIFSet and DAIFClr mask four classes independently: Debug, SError, IRQ and FIQ. A driver can therefore block ordinary interrupts while leaving the fast interrupt live, which the others cannot express. | |
| RISC-V | one instruction | No dedicated instruction. The MIE bit in mstatus is cleared or set with an ordinary atomic CSR read-modify-write, which returns the previous value in the same instruction and so makes save-and-restore natural rather than an extra step. | |
| PowerISA | one instruction | The EE bit lives in the MSR and is written with MTMSR, the same instruction used for every other machine-state change, so masking interrupts is not a special case. |
Other operations
Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Instruction Cache Synchronisation Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load and Store Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Materialise a Large Constant Memory Barrier / Fence Multiply High No Operation PC-Relative Address Population Count Read Cycle Counter Return From Exception Rotate Left Sign Extend Byte Speculation Barrier Spin-Wait Hint Stack Push and Pop System Call