Cache Prefetch Hint
Hint that a cache line should be brought closer to the core before it is used.
Memory System
Semantics
A performance hint with no architectural effect: it may be ignored, and it never faults on an inaccessible address.
| Architecture | Instructions | Expressed as | How this architecture does it |
|---|---|---|---|
| x86 | one instruction | The suffix selects a cache-level hint: T0 through T2 target the cache hierarchy, NTA marks the data as non-temporal. | |
| ARM | one instruction | One instruction with a structured hint operand encoding type (load/store/instruction), target level, and retention policy, for example PRFM PLDL1KEEP. | |
| RISC-V | one instruction | Zicbop. The read and write forms are separate instructions rather than a hint field. | |
| PowerISA | one instruction | dcbt hints a read and dcbtst a forthcoming write; both are base data cache block touch instructions. |
Other operations
Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Enable and Disable Interrupts Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Instruction Cache Synchronisation Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load and Store Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Materialise a Large Constant Memory Barrier / Fence Multiply High No Operation PC-Relative Address Population Count Read Cycle Counter Return From Exception Rotate Left Sign Extend Byte Speculation Barrier Spin-Wait Hint Stack Push and Pop System Call