Base Instructions
159 ARM instructions in this extension - showing 100 per page, page 1 of 2 - click any row for encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Summary |
|---|---|---|---|
| adc | ADC <Wd>, <Wn>, <Wm> | Data Processing (3-source) | Adds two register values and the Carry flag. |
| adc | ADC <Xd>, <Xn>, <Xm> | Data Processing (3-source) | Adds two 64-bit register values and the Carry flag. |
| adcs | ADCS <Wd>, <Wn>, <Wm> | Data Processing (3-source) | Adds two register values and Carry, updating NZCV flags. |
| adcs | ADCS <Xd>, <Xn>, <Xm> | Data Processing (3-source) | Adds two 64-bit register values and Carry, updating NZCV flags. |
| add | ADD <Wd|Wsp>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}} | Data Processing (Register) | Adds a register value and a sign/zero-extended register value. |
| add | ADD <Xd|SP>, <Xn|SP>, <R><m> {, <extend> {#<amount>}} | Data Processing (Register) | Adds a 64-bit register and an extended register value. |
| add | ADD <Wd|Wsp>, <Wn|Wsp>, #<imm> {, lsl #<shift>} | Data Processing (Immediate) | Adds a register value and an immediate value. |
| add | ADD <Xd|SP>, <Xn|SP>, #<imm> {, lsl #<shift>} | Data Processing (Immediate) | Adds a 64-bit register value and an immediate value. |
| add | ADD <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Data Processing (Register) | Adds a register value and a shifted register value. |
| add | ADD <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Data Processing (Register) | Adds a 64-bit register value and a shifted register value. |
| adds | ADDS <Wd>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}} | Data Processing (Register) | Adds and updates flags (Extended Register). |
| adds | ADDS <Xd>, <Xn|SP>, <R><m> {, <extend> {#<amount>}} | Data Processing (Register) | Adds and updates flags (Extended Register 64-bit). |
| adds | ADDS <Wd>, <Wn|Wsp>, #<imm> {, lsl #<shift>} | Data Processing (Immediate) | Adds immediate and updates flags. |
| adds | ADDS <Xd>, <Xn|SP>, #<imm> {, lsl #<shift>} | Data Processing (Immediate) | Adds immediate and updates flags (64-bit). |
| adds | ADDS <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Data Processing (Register) | Adds shifted register and updates flags. |
| adds | ADDS <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Data Processing (Register) | Adds shifted register and updates flags (64-bit). |
| adr | ADR <Xd>, <label> | PC-rel | Calculates the address of a label (PC +/- 1MB range). |
| adrp | ADRP <Xd>, <label> | PC-rel | Calculates page address of a label (PC +/- 4GB range). |
| and | AND <Wd|Wsp>, <Wn>, #<imm> | Logical (Immediate) | Bitwise AND with logical immediate. |
| and | AND <Xd|SP>, <Xn>, #<imm> | Logical (Immediate) | Bitwise AND with logical immediate (64-bit). |
| and | AND <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Bitwise AND with shifted register. |
| and | AND <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Logical (Register) | Bitwise AND with shifted register (64-bit). |
| ands | ANDS <Wd>, <Wn>, #<imm> | Logical (Immediate) | Bitwise AND immediate, updates flags. |
| ands | ANDS <Xd>, <Xn>, #<imm> | Logical (Immediate) | Bitwise AND immediate, updates flags (64-bit). |
| ands | ANDS <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Bitwise AND shifted register, updates flags. |
| ands | ANDS <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Logical (Register) | Bitwise AND shifted register, updates flags (64-bit). |
| asr | ASR <Wd>, <Wn>, #<shift> | Data Processing (Immediate) | Arithmetic shift right by immediate. |
| asr | ASR <Xd>, <Xn>, #<shift> | Data Processing (Immediate) | Arithmetic shift right by immediate (64-bit). |
| asr | ASR <Wd>, <Wn>, <Wm> | Data Processing (Register) | Arithmetic shift right by register value. |
| asr | ASR <Xd>, <Xn>, <Xm> | Data Processing (Register) | Arithmetic shift right by register value (64-bit). |
| b | B <label> | Branch | Unconditional branch to label. |
| b.cond | B.cond <label> | Branch | Branch if condition is met (e.g., B.EQ, B.NE). |
| bfm | BFM <Wd>, <Wn>, #<immr>, #<imms> | Bitfield | Moves a bitfield from source to destination. |
| bfm | BFM <Xd>, <Xn>, #<immr>, #<imms> | Bitfield | Moves a bitfield from source to destination (64-bit). |
| bic | BIC <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | ANDs register with NOT of shifted register (AND NOT). |
| bic | BIC <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Logical (Register) | ANDs register with NOT of shifted register (64-bit). |
| bics | BICS <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Performs BIC and updates flags. |
| bics | BICS <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Logical (Register) | Performs BIC and updates flags (64-bit). |
| bl | BL <label> | Branch | Function call. Branches to label and stores return address in LR (X30). |
| blr | BLR <Xn> | Branch (Reg) | Indirect function call. Branches to address in Xn and stores return in LR. |
| br | BR <Xn> | Branch (Reg) | Indirect branch to address in Xn. |
| brk | BRK #<imm> | Exception | Generates a Breakpoint instruction exception. |
| cbnz | CBNZ <Wt>, <label> | Branch | Branches if register is not zero. |
| cbnz | CBNZ <Xt>, <label> | Branch | Branches if 64-bit register is not zero. |
| cbz | CBZ <Wt>, <label> | Branch | Branches if register is zero. |
| cbz | CBZ <Xt>, <label> | Branch | Branches if 64-bit register is zero. |
| ccmn | CCMN <Wn>, #<imm>, #<nzcv>, <cond> | Cond Comp | Compares register with negative immediate if condition is true. |
| ccmn | CCMN <Xn>, #<imm>, #<nzcv>, <cond> | Cond Comp | Compares 64-bit register with negative immediate if condition is true. |
| ccmn | CCMN <Wn>, <Wm>, #<nzcv>, <cond> | Cond Comp | Compares two registers (negated) if condition is true. |
| ccmp | CCMP <Wn>, #<imm>, #<nzcv>, <cond> | Cond Comp | Compares register with immediate if condition is true. |
| ccmp | CCMP <Wn>, <Wm>, #<nzcv>, <cond> | Cond Comp | Compares two registers if condition is true. |
| cinc | CINC <Wd>, <Wn>, <cond> | Cond Select | Increment register if condition is true, else copy. (Alias for CSINC) |
| cinv | CINV <Wd>, <Wn>, <cond> | Cond Select | Invert register bits if condition is true, else copy. (Alias for CSINV) |
| cls | CLS <Wd>, <Wn> | Data Processing | Counts number of consecutive sign bits. |
| clz | CLZ <Wd>, <Wn> | Data Processing | Counts number of consecutive zeros. |
| cmn | CMN <Wn>, #<imm> | Data Processing | Adds register and immediate, updates flags (discard result). (Alias for ADDS) |
| cmp | CMP <Wn>, #<imm> | Data Processing | Subtracts immediate from register, updates flags (discard result). (Alias for SUBS) |
| cneg | CNEG <Wd>, <Wn>, <cond> | Cond Select | Negate register if condition is true, else copy. (Alias for CSNEG) |
| csdb | CSDB | System Hint | Prevents speculative data consumption. |
| csel | CSEL <Wd>, <Wn>, <Wm>, <cond> | Cond Select | Selects between two registers based on condition. |
| cset | CSET <Wd>, <cond> | Cond Select | Sets register to 1 if condition true, else 0. (Alias for CSINC) |
| csinc | CSINC <Wd>, <Wn>, <Wm>, <cond> | Cond Select | Selects Wn if cond true, else (Wm + 1). |
| csinv | CSINV <Wd>, <Wn>, <Wm>, <cond> | Cond Select | Selects Wn if cond true, else NOT Wm. |
| csneg | CSNEG <Wd>, <Wn>, <Wm>, <cond> | Cond Select | Selects Wn if cond true, else -Wm. |
| dgh | DGH | System Hint | Hints that multiple memory accesses should be merged. |
| dmb | DMB <option> | System | Ensures memory access ordering. |
| dsb | DSB <option> | System | Ensures completion of memory accesses. |
| eon | EON <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | XORs register with NOT of shifted register (XNOR). |
| eon | EON <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Logical (Register) | XORs 64-bit register with NOT of shifted register. |
| eor | EOR <Wd|Wsp>, <Wn>, #<imm> | Logical (Immediate) | XORs register with immediate. |
| eor | EOR <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | XORs two registers. |
| eret | ERET | System | Returns from an exception. |
| extr | EXTR <Wd>, <Wn>, <Wm>, #<lsb> | Data Processing | Extracts a register from a pair of registers. |
| extr | EXTR <Xd>, <Xn>, <Xm>, #<lsb> | Data Processing | Extracts a 64-bit register from a pair. |
| hint | HINT #<imm> | System | Provides a hint to the processor (e.g., NOP, YIELD). |
| hlt | HLT #<imm> | Exception | Enters Halting debug mode. |
| isb | ISB {<option>} | System | Flushes the pipeline and prefetches. |
| ldnp | LDNP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>] | Load/Store Pair | Loads two words, hinting non-temporal data (no caching). |
| ldp | LDP <Wt1>, <Wt2>, [<Xn|SP>], #<imm> | Load/Store Pair | Loads two words from memory. |
| ldp | LDP <Xt1>, <Xt2>, [<Xn|SP>], #<imm> | Load/Store Pair | Loads two 64-bit doublewords from memory. |
| ldpsw | LDPSW <Xt1>, <Xt2>, [<Xn|SP>, #<imm>] | Load/Store Pair | Loads two words and sign-extends them to 64-bit. |
| ldr | LDR <Wt>, [<Xn|SP>, #<pimm>] | Load/Store Imm | Loads a word from memory (Immediate offset). |
| ldr | LDR <Wt>, <label> | Load Literal | Loads a word from a PC-relative address. |
| ldr | LDR <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] | Load/Store Reg | Loads a word from memory (Register offset). |
| ldrb | LDRB <Wt>, [<Xn|SP>, #<pimm>] | Load/Store | Loads a byte from memory (zero-extended) using immediate offset. |
| ldrb | LDRB <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] | Load/Store | Loads a byte from memory (zero-extended) using register offset. |
| ldrh | LDRH <Wt>, [<Xn|SP>, #<pimm>] | Load/Store | Loads a halfword from memory (zero-extended). |
| ldrh | LDRH <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] | Load/Store | Loads a halfword from memory (zero-extended) using register offset. |
| ldrsb | LDRSB <Wt>, [<Xn|SP>, #<pimm>] | Load/Store | Loads a byte and sign-extends it to 32-bits. |
| ldrsb | LDRSB <Xt>, [<Xn|SP>, #<pimm>] | Load/Store | Loads a byte and sign-extends it to 64-bits. |
| ldrsw | LDRSW <Xt>, [<Xn|SP>, #<pimm>] | Load/Store | Loads a word and sign-extends it to 64-bits. |
| ldrsw | LDRSW <Xt>, <label> | Load Literal | Loads a word from PC-relative address and sign-extends to 64-bits. |
| ldtr | LDTR <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Loads a word as if in EL0 (User mode). |
| ldur | LDUR <Wt>, [<Xn|SP>, #<simm>] | Load/Store | Loads a word using an unscaled immediate offset. |
| lsl | LSLV <Wd>, <Wn>, <Wm> | Data Processing | Shifts register left by variable amount. |
| lsr | LSRV <Wd>, <Wn>, <Wm> | Data Processing | Shifts register right by variable amount. |
| madd | MADD <Wd>, <Wn>, <Wm>, <Wa> | Data Processing | Calculates (Ra + (Rn * Rm)). |
| madd | MADD <Xd>, <Xn>, <Xm>, <Xa> | Data Processing | Calculates (Xa + (Xn * Xm)). |
| movk | MOVK <Wd>, #<imm16> {, lsl #<shift>} | Data Processing | Inserts a 16-bit immediate into a register, keeping other bits unchanged. |
| movn | MOVN <Wd>, #<imm16> {, lsl #<shift>} | Data Processing | Moves inverted 16-bit immediate to register. |