asr
Arithmetic Shift Right (Register 64-bit)
ASR <Xd>, <Xn>, <Xm>
Arithmetic shift right by register value (64-bit).
Details
Arithmetic shift right of Xn by the number of bits specified in the least significant byte of Xm, writing the result to Xd. The sign bit is replicated into vacated bit positions. NZCV flags are not affected by this instruction in AArch64.
Pseudocode Operation
shift_amount ← Xm[7:0]
if shift_amount >= 64 then
if Xn[63] == 1 then Xd ← 0xFFFFFFFFFFFFFFFF else Xd ← 0
else
Xd ← Xn >> shift_amount (arithmetic)Example
ASR x0, x1, x2
Encoding
Binary Layout
1
0
0
11010110
Rm
0010
10
Rn
Rd
Operands
-
Xd
Destination 64-bit integer register -
Xn
First source / base 64-bit integer register -
Xm
Shift Reg
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x1AC02800 | ASR <Wd>, <Wn>, <Wm> | A64 | 0 | 0 | 0 | 11010110 | Rm | 0010 | 10 | Rn | Rd | ||
| 0x9AC02800 | ASR <Xd>, <Xn>, <Xm> | A64 | 1 | 0 | 0 | 11010110 | Rm | 0010 | 10 | Rn | Rd | ||
| 0x13007C00 | ASR <Wd>, <Wn>, #<shift> | A64 | 0 | 00 | 100110 | 0 | immr | 011111 | Rn | Rd | ||
| 0x9340FC00 | ASR <Xd>, <Xn>, #<shift> | A64 | 1 | 00 | 100110 | 1 | immr | 111111 | Rn | Rd | ||
| 0x04008000 | ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const> | A64 | 00000100 | tszh | 00 | 0 | 0 | 0 | 0 | 100 | Pg | tszl | imm3 | Zdn | ||
| 0x04188000 | ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D | A64 | 00000100 | size | 011 | 0 | 0 | 0 | 100 | Pg | Zm | Zdn | ||
| 0x04108000 | ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | A64 | 00000100 | size | 010 | 0 | 0 | 0 | 100 | Pg | Zm | Zdn | ||
| 0x04209000 | ASR <Zd>.<T>, <Zn>.<T>, #<const> | A64 | 00000100 | tszh | 1 | tszl | imm3 | 1001 | 0 | 0 | Zn | Zd | ||
| 0x04208000 | ASR <Zd>.<T>, <Zn>.<T>, <Zm>.D | A64 | 00000100 | size | 1 | Zm | 1000 | 0 | 0 | Zn | Zd |
Description
Arithmetic Shift Right (register) shifts a register value right by a variable number of bits, shifting in copies of its sign bit, and writes the result to the destination register. The remainder obtained by dividing the second source register by the data size defines the number of bits by which the first source register is right-shifted.