rcwswppal

Read Check Write (Acquire-Release)

RCWAL <Xt>, <Xt+1>, [<Xn>]

Read Check Write with Acquire and Release semantics.

Details

Atomically reads a 128-bit translation table descriptor from memory with full Acquire-Release memory ordering semantics (FEAT_THE). The instruction enforces both Acquire (on the read) and Release (implicit for conditional update) constraints, providing full mutual exclusion semantics. Available only in AArch64 with 128-bit alignment requirement.

Pseudocode Operation

address ← Xn; data ← Mem[address, 16]; AcquireSemantics(); ValidateAndProcess(data); if validated then Mem[address, 16] ← data; ReleaseSemantics(); Xt ← data[63:0]; Xt+1 ← data[127:64];

Example

RCWAL x3, Xt+1, [x1]

Encoding

Binary Layout
0
0
011001
1
1
1
Rt2
1
010
00
Rn
Rt
 
Format Atomic
Opcode 0x19E0A000
Extension FEAT_THE (Hardening)

Operands

  • Xt
    Data/Status
  • Xn
    Address

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x19E0A000 RCWSWPPAL <Xt1>, <Xt2>, [<Xn|SP>] A64 0 | 0 | 011001 | 1 | 1 | 1 | Rt2 | 1 | 010 | 00 | Rn | Rt

Description

Read Check Write Swap quadword in memory atomically loads a 128-bit quadword from a memory location, and conditionally stores the value held in a pair of registers back to the same memory location. Storing back to memory is conditional on RCW Checks. The value initially loaded from memory is returned in the same pair of registers. This instruction updates the condition flags based on the result of the update of memory.

Operation

if !IsD128Enabled(PSTATE.EL) then UNDEFINED;
bits(64) address;
bits(64) value1;
bits(64) value2;
bits(128) newdata;
bits(128) readdata;
bits(4) nzcv;

AccessDescriptor accdesc = CreateAccDescRCW(MemAtomicOp_SWP, FALSE, acquire, release, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

value1 = X[t, 64];
value2 = X[t2, 64];

newdata = if BigEndian(accdesc.acctype) then value1:value2 else value2:value1;

bits(128) compdata = bits(128) UNKNOWN;    // Irrelevant when not executing CAS
(nzcv, readdata) = MemAtomicRCW(address, compdata, newdata, accdesc);

PSTATE.<N,Z,C,V> = nzcv;
if rt_unknown then
    readdata = bits(128) UNKNOWN;

if BigEndian(accdesc.acctype) then
    X[t, 64] = readdata<127:64>;
    X[t2, 64] = readdata<63:0>;
else
    X[t, 64] = readdata<63:0>;
    X[t2, 64] = readdata<127:64>;