rcwswppal

Read Check Write Swap Pair (Acquire-Release)

RCWSWPPAL <Xt>, <Xt+1>, [<Xn>]

Atomically swaps a 128-bit register pair with a checked descriptor in memory, with Acquire and Release semantics (Translation Hardening).

Pseudocode Operation

address ← Xn; data ← Mem[address, 16]; AcquireSemantics(); ValidateAndProcess(data); if validated then Mem[address, 16] ← data; ReleaseSemantics(); Xt ← data[63:0]; Xt+1 ← data[127:64];

Example

RCWSWPPAL x2, x3, [x1]

Encoding

Binary Layout

0

31

0

30

011001

29:24

1

23

1

22

1

21

Rt2

20:16

1

15

010

14:12

00

11:10

Rn

9:5

Rt

4:0

 

Format Atomic

Opcode 0x19E0A000

Extension FEAT_THE (Hardening)

Operands

• Xt
  Data/Status
• Xt+1
  Second register of the data pair
• Xn
  Address

Related

More in FEAT_THE (Hardening)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x19E0A000	RCWSWPPAL <Xt1>, <Xt2>, [<Xn|SP>]		A64		0 | 0 | 011001 | 1 | 1 | 1 | Rt2 | 1 | 010 | 00 | Rn | Rt

Description

Read Check Write Swap quadword in memory atomically loads a 128-bit quadword from a memory location, and conditionally stores the value held in a pair of registers back to the same memory location. Storing back to memory is conditional on RCW Checks. The value initially loaded from memory is returned in the same pair of registers. This instruction updates the condition flags based on the result of the update of memory.

Operation

if !IsD128Enabled(PSTATE.EL) then UNDEFINED;
bits(64) address;
bits(64) value1;
bits(64) value2;
bits(128) newdata;
bits(128) readdata;
bits(4) nzcv;

AccessDescriptor accdesc = CreateAccDescRCW(MemAtomicOp_SWP, FALSE, acquire, release, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

value1 = X[t, 64];
value2 = X[t2, 64];

newdata = if BigEndian(accdesc.acctype) then value1:value2 else value2:value1;

bits(128) compdata = bits(128) UNKNOWN;    // Irrelevant when not executing CAS
(nzcv, readdata) = MemAtomicRCW(address, compdata, newdata, accdesc);

PSTATE.<N,Z,C,V> = nzcv;
if rt_unknown then
    readdata = bits(128) UNKNOWN;

if BigEndian(accdesc.acctype) then
    X[t, 64] = readdata<127:64>;
    X[t2, 64] = readdata<63:0>;
else
    X[t, 64] = readdata<63:0>;
    X[t2, 64] = readdata<127:64>;