vsub

Vector Subtract (Integer)

VSUB<c>.<dt> <Qd>, <Qn>, <Qm>

Subtracts integer elements.

Details

Vector Subtract (Integer) performs element-wise subtraction of two NEON 128-bit registers, subtracting corresponding integer elements of size 8, 16, 32, or 64 bits. The instruction executes in Q-register (128-bit) mode and wraps on underflow without setting flags. This is a NEON SIMD instruction available in both A32 and T32 states when NEON is supported.

Pseudocode Operation

for each element i in Qd:
  Qd[i] ← Qn[i] - Qm[i]

Example

VSUB.dt q0, q1, q2

Encoding

Binary Layout
1111001
0
0
D
1
sz
Vn
Vd
1101
N
1
M
0
Vm
 
Format NEON 3-Reg
Opcode 0xF2200D40
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2200D00 VSUB{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> A32 1111001 | 0 | 0 | D | 1 | sz | Vn | Vd | 1101 | N | 0 | M | 0 | Vm
0xF2200D40 VSUB{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> A32 1111001 | 0 | 0 | D | 1 | sz | Vn | Vd | 1101 | N | 1 | M | 0 | Vm
0x0E300940 VSUB{<c>}{<q>}.F16 {<Sd>,} <Sn>, <Sm> A32 cond | 1110 | 0 | D | 11 | Vn | Vd | 10 | 01 | N | 1 | M | 0 | Vm
0x0E300A40 VSUB{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm> A32 cond | 1110 | 0 | D | 11 | Vn | Vd | 10 | 10 | N | 1 | M | 0 | Vm
0x0E300B40 VSUB{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm> A32 cond | 1110 | 0 | D | 11 | Vn | Vd | 10 | 11 | N | 1 | M | 0 | Vm
0xEF200D00 VSUB{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> T32 111 | 0 | 11110 | D | 1 | sz | Vn | Vd | 1101 | N | 0 | M | 0 | Vm
0xEF200D40 VSUB{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> T32 111 | 0 | 11110 | D | 1 | sz | Vn | Vd | 1101 | N | 1 | M | 0 | Vm
0xEE300940 VSUB{<c>}{<q>}.F16 {<Sd>,} <Sn>, <Sm> T32 11101110 | 0 | D | 11 | Vn | Vd | 10 | 01 | N | 1 | M | 0 | Vm
0xEE300A40 VSUB{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm> T32 11101110 | 0 | D | 11 | Vn | Vd | 10 | 10 | N | 1 | M | 0 | Vm
0xEE300B40 VSUB{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm> T32 11101110 | 0 | D | 11 | Vn | Vd | 10 | 11 | N | 1 | M | 0 | Vm
0xF3000800 VSUB{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> A32 1111001 | 1 | 0 | D | size | Vn | Vd | 1000 | N | 0 | M | 0 | Vm
0xF3000840 VSUB{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> A32 1111001 | 1 | 0 | D | size | Vn | Vd | 1000 | N | 1 | M | 0 | Vm
0xFF000800 VSUB{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> T32 111 | 1 | 11110 | D | size | Vn | Vd | 1000 | N | 0 | M | 0 | Vm
0xFF000840 VSUB{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> T32 111 | 1 | 11110 | D | size | Vn | Vd | 1000 | N | 1 | M | 0 | Vm

Description

Vector Subtract (floating-point) subtracts the elements of one vector from the corresponding elements of another vector, and places the results in the destination vector. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
    if advsimd then  // Advanced SIMD instruction
        for r = 0 to regs-1
            for e = 0 to elements-1
                Elem[D[d+r],e,esize] = FPSub(Elem[D[n+r],e,esize], Elem[D[m+r],e,esize],
                                             StandardFPSCRValue());
    else             // VFP instruction
        case esize of
            when 16
                S[d] = Zeros(16) : FPSub(S[n]<15:0>, S[m]<15:0>, FPSCR[]);
            when 32
                S[d] = FPSub(S[n], S[m], FPSCR[]);
            when 64
                D[d] = FPSub(D[n], D[m], FPSCR[]);