vmov

Vector Move (Double)

VMOV<c>.F64 <Dd>, <Dm>

Moves data between Double registers.

Details

Copies a 64-bit double-precision floating-point value from Dm to Dd with no arithmetic or rounding. This is a register-to-register move within the VFP register file. No condition flags are affected, and this instruction executes unconditionally (though it respects the condition code in A32/T32).

Pseudocode Operation

Dd ← Dm;

Example

VMOV.F64 d0, d2

Encoding

Binary Layout
cond
11101
D
11
0
000
Vd
10
size
0
1
M
0
Vm
 
Format VFP Move
Opcode 0x0EB00A40
Extension VFP (Float)

Operands

  • Dd
    Destination 64-bit SIMD/FP register
  • Dm
    Second source 64-bit SIMD/FP register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0C400B10 VMOV{<c>}{<q>} <Dm>, <Rt>, <Rt2> A32 cond | 11000 | 1 | 0 | 0 | Rt2 | Rt | 10 | 11 | 00 | M | 1 | Vm
0x0C500B10 VMOV{<c>}{<q>} <Rt>, <Rt2>, <Dm> A32 cond | 11000 | 1 | 0 | 1 | Rt2 | Rt | 10 | 11 | 00 | M | 1 | Vm
0xEC400B10 VMOV{<c>}{<q>} <Dm>, <Rt>, <Rt2> T32 111011000 | 1 | 0 | 0 | Rt2 | Rt | 10 | 11 | 00 | M | 1 | Vm
0xEC500B10 VMOV{<c>}{<q>} <Rt>, <Rt2>, <Dm> T32 111011000 | 1 | 0 | 1 | Rt2 | Rt | 10 | 11 | 00 | M | 1 | Vm
0x0E000910 VMOV{<c>}{<q>}.F16 <Sn>, <Rt> A32 cond | 1110000 | 0 | Vn | Rt | 1001 | N | 0 | 0 | 1 | 0 | 0 | 0 | 0
0x0E100910 VMOV{<c>}{<q>}.F16 <Rt>, <Sn> A32 cond | 1110000 | 1 | Vn | Rt | 1001 | N | 0 | 0 | 1 | 0 | 0 | 0 | 0
0xEE000910 VMOV{<c>}{<q>}.F16 <Sn>, <Rt> T32 11101110000 | 0 | Vn | Rt | 1001 | N | 0 | 0 | 1 | 0 | 0 | 0 | 0
0xEE100910 VMOV{<c>}{<q>}.F16 <Rt>, <Sn> T32 11101110000 | 1 | Vn | Rt | 1001 | N | 0 | 0 | 1 | 0 | 0 | 0 | 0
0xF2800010 VMOV{<c>}{<q>}.I32 <Dd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 0 | 0 | 1 | imm4
0xF2800050 VMOV{<c>}{<q>}.I32 <Qd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 1 | 0 | 1 | imm4
0x0EB00900 VMOV{<c>}{<q>}.F16 <Sd>, #<imm> A32 cond | 11101 | D | 11 | imm4H | Vd | 10 | 01 | 0 | 0 | 0 | 0 | imm4L
0x0EB00A00 VMOV{<c>}{<q>}.F32 <Sd>, #<imm> A32 cond | 11101 | D | 11 | imm4H | Vd | 10 | 10 | 0 | 0 | 0 | 0 | imm4L
0x0EB00B00 VMOV{<c>}{<q>}.F64 <Dd>, #<imm> A32 cond | 11101 | D | 11 | imm4H | Vd | 10 | 11 | 0 | 0 | 0 | 0 | imm4L
0xF2800810 VMOV{<c>}{<q>}.I16 <Dd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 0 | 0 | 1 | imm4

Description

Copy between FP registers copies the contents of one FP register to another. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
    if single_register then
        S[d] = S[m];
    else
        for r = 0 to regs-1
            D[d+r] = D[m+r];