vstm

Vector Store Multiple (VFP)

VSTM<c><mode> <Rn>{!}, <list>

Stores multiple VFP registers to memory.

Pseudocode Operation

address ← Rn; for i = 0 to (list_count - 1) do; [address] ← Vriestlist[i]; address ← address + (register_size / 8); end; if !(!) then Rn ← address;

Example

VSTMia r1!, {r0-r3

Encoding

Binary Layout
cond
31:28
110
27:25
0
24
1
23
D
22
W
21
0
20
Rn
19:16
Vd
15:12
10
11:10
10
9:8
imm8
7:0
 
Format VFP Store Multiple
Opcode 0x0C800A00
Extension VFP (Float)

Operands

  • Rn
    First source / base general-purpose register
  • list
    Registers

Related

More in VFP (Float)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0C800B00 VSTM{<c>}{<q>}{.<size>} <Rn>{!}, <dreglist> A32 cond | 110 | 0 | 1 | D | W | 0 | Rn | Vd | 10 | 11 | imm8<7:1> | 0
0x0C800A00 VSTM{<c>}{<q>}{.<size>} <Rn>{!}, <sreglist> A32 cond | 110 | 0 | 1 | D | W | 0 | Rn | Vd | 10 | 10 | imm8
0xEC800B00 VSTM{<c>}{<q>}{.<size>} <Rn>{!}, <dreglist> T32 1110110 | 0 | 1 | D | W | 0 | Rn | Vd | 10 | 11 | imm8<7:1> | 0
0xEC800A00 VSTM{<c>}{<q>}{.<size>} <Rn>{!}, <sreglist> T32 1110110 | 0 | 1 | D | W | 0 | Rn | Vd | 10 | 10 | imm8

Description

Store multiple SIMD&FP registers stores multiple registers from the Advanced SIMD and floating-point register file to consecutive memory locations using an address from a general-purpose register. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckVFPEnabled(TRUE);
    address = if add then R[n] else R[n]-imm32;
    for r = 0 to regs-1
        if single_regs then
            MemA[address,4] = S[d+r];
            address = address+4;
        else
            // Store as two word-aligned words in the correct order for current endianness.
            if BigEndian(AccessType_ASIMD) then
                MemA[address,4] =  D[d+r]<63:32>;
                MemA[address+4,4] =  D[d+r]<31:0>;
            else
                MemA[address,4] = D[d+r]<31:0>;
                MemA[address+4,4] = D[d+r]<63:32>;

            address = address+8;

    if wback then R[n] = if add then R[n]+imm32 else R[n]-imm32;