vcvtm

Vector Convert to Integer (Minus Infinity)

VCVTM<c>.<dt>.F32 <Qd>, <Qm>

Converts float to integer, rounding towards -Inf (Floor).

Details

Converts floating-point values in a NEON vector to signed integers, rounding towards negative infinity (floor). This is a NEON SIMD instruction that operates on 32-bit floating-point elements and produces integer results. No condition flags are affected by this instruction.

Pseudocode Operation

for i = 0 to elements-1
  Qd[i] ← RoundTowardsMinusInfinity(Qm[i])

Example

VCVTM.dt.F32 q0, q2

Encoding

Binary Layout
111111101
D
111
1
11
Vd
10
10
op
1
M
0
Vm
 
Format NEON 2-Reg
Opcode 0xFEBF0A40
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3B30300 VCVTM{<q>}.<dt>.<dt2> <Dd>, <Dm> A32 111100111 | D | 11 | size | 11 | Vd | 0 | 0 | 11 | op | 0 | M | 0 | Vm
0xF3B30340 VCVTM{<q>}.<dt>.<dt2> <Qd>, <Qm> A32 111100111 | D | 11 | size | 11 | Vd | 0 | 0 | 11 | op | 1 | M | 0 | Vm
0xFFB30300 VCVTM{<q>}.<dt>.<dt2> <Dd>, <Dm> T32 111111111 | D | 11 | size | 11 | Vd | 0 | 0 | 11 | op | 0 | M | 0 | Vm
0xFFB30340 VCVTM{<q>}.<dt>.<dt2> <Qd>, <Qm> T32 111111111 | D | 11 | size | 11 | Vd | 0 | 0 | 11 | op | 1 | M | 0 | Vm
0xFEBF0940 VCVTM{<q>}.<dt>.F16 <Sd>, <Sm> A32 111111101 | D | 111 | 1 | 11 | Vd | 10 | 01 | op | 1 | M | 0 | Vm
0xFEBF0A40 VCVTM{<q>}.<dt>.F32 <Sd>, <Sm> A32 111111101 | D | 111 | 1 | 11 | Vd | 10 | 10 | op | 1 | M | 0 | Vm
0xFEBF0B40 VCVTM{<q>}.<dt>.F64 <Sd>, <Dm> A32 111111101 | D | 111 | 1 | 11 | Vd | 10 | 11 | op | 1 | M | 0 | Vm

Description

Convert floating-point to integer with Round towards -Infinity converts a value in a register from floating-point to a 32-bit integer using the Round towards -Infinity rounding mode, and places the result in a second register. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
case esize of
    when 16
        S[d] = FPToFixed(S[m]<15:0>, 0, unsigned, FPSCR[], rounding, 32);
    when 32
        S[d] = FPToFixed(S[m], 0, unsigned, FPSCR[], rounding, 32);
    when 64
        S[d] = FPToFixed(D[m], 0, unsigned, FPSCR[], rounding, 32);