vmov

Vector Move (Double <-> 2xGPR)

VMOV<c> <Rt>, <Rt2>, <Dm>

Moves a Double register to/from two Core registers.

Details

Transfers a 64-bit value between a VFP double-precision register (Dm) and two consecutive ARM core registers (Rt for bits [31:0], Rt2 for bits [63:32]). Direction is determined by the opcode bit pattern: from core to VFP or VFP to core. No condition flags are affected.

Pseudocode Operation

if direction == 'core_to_vfp' then Dm ← Rt2 || Rt; else Rt ← Dm[31:0]; Rt2 ← Dm[63:32];

Example

VMOV r3, r4, d2

Encoding

Binary Layout
cond
11000
1
0
0
Rt2
Rt
10
11
00
M
1
Vm
 
Format VFP Transfer
Opcode 0x0C400B10
Extension VFP (Float)

Operands

  • Rt
    Low
  • Rt2
    High
  • Dm
    VFP

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0C400B10 VMOV{<c>}{<q>} <Dm>, <Rt>, <Rt2> A32 cond | 11000 | 1 | 0 | 0 | Rt2 | Rt | 10 | 11 | 00 | M | 1 | Vm
0x0C500B10 VMOV{<c>}{<q>} <Rt>, <Rt2>, <Dm> A32 cond | 11000 | 1 | 0 | 1 | Rt2 | Rt | 10 | 11 | 00 | M | 1 | Vm
0xEC400B10 VMOV{<c>}{<q>} <Dm>, <Rt>, <Rt2> T32 111011000 | 1 | 0 | 0 | Rt2 | Rt | 10 | 11 | 00 | M | 1 | Vm
0xEC500B10 VMOV{<c>}{<q>} <Rt>, <Rt2>, <Dm> T32 111011000 | 1 | 0 | 1 | Rt2 | Rt | 10 | 11 | 00 | M | 1 | Vm
0x0E000910 VMOV{<c>}{<q>}.F16 <Sn>, <Rt> A32 cond | 1110000 | 0 | Vn | Rt | 1001 | N | 0 | 0 | 1 | 0 | 0 | 0 | 0
0x0E100910 VMOV{<c>}{<q>}.F16 <Rt>, <Sn> A32 cond | 1110000 | 1 | Vn | Rt | 1001 | N | 0 | 0 | 1 | 0 | 0 | 0 | 0
0xEE000910 VMOV{<c>}{<q>}.F16 <Sn>, <Rt> T32 11101110000 | 0 | Vn | Rt | 1001 | N | 0 | 0 | 1 | 0 | 0 | 0 | 0
0xEE100910 VMOV{<c>}{<q>}.F16 <Rt>, <Sn> T32 11101110000 | 1 | Vn | Rt | 1001 | N | 0 | 0 | 1 | 0 | 0 | 0 | 0
0xF2800010 VMOV{<c>}{<q>}.I32 <Dd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 0 | 0 | 1 | imm4
0xF2800050 VMOV{<c>}{<q>}.I32 <Qd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 1 | 0 | 1 | imm4
0x0EB00900 VMOV{<c>}{<q>}.F16 <Sd>, #<imm> A32 cond | 11101 | D | 11 | imm4H | Vd | 10 | 01 | 0 | 0 | 0 | 0 | imm4L
0x0EB00A00 VMOV{<c>}{<q>}.F32 <Sd>, #<imm> A32 cond | 11101 | D | 11 | imm4H | Vd | 10 | 10 | 0 | 0 | 0 | 0 | imm4L
0x0EB00B00 VMOV{<c>}{<q>}.F64 <Dd>, #<imm> A32 cond | 11101 | D | 11 | imm4H | Vd | 10 | 11 | 0 | 0 | 0 | 0 | imm4L
0xF2800810 VMOV{<c>}{<q>}.I16 <Dd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 0 | 0 | 1 | imm4

Description

Copy two general-purpose registers to or from a SIMD&FP register copies two words from two general-purpose registers into a doubleword register in the Advanced SIMD and floating-point register file, or from a doubleword register in the Advanced SIMD and floating-point register file to two general-purpose registers. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckVFPEnabled(TRUE);
    if to_arm_registers then
        R[t] = D[m]<31:0>;
        R[t2] = D[m]<63:32>;
    else
        D[m]<31:0> = R[t];
        D[m]<63:32> = R[t2];