stlrb

Store-Release Register Byte

STLRB <Wt>, [<Xn|SP>]

Stores a byte with Release semantics.

Details

Stores the least significant byte of Wt to memory at the address specified by Xn (or SP), with Release semantics for synchronization. The Release semantics ensure that all memory operations before this instruction are visible to observers before the byte store completes. No condition flags are affected. This instruction is AArch64-only and requires the Load-Acquire/Store-Release extension.

Pseudocode Operation

address ← Xn
MemoryOrder(Release)
[address] ← Wt[7:0]

Example

STLRB w3, [x1]

Encoding

Binary Layout
00
0010001
0
0
11111
1
11111
Rn
Rt
 
Format Load/Store
Opcode 0x089FFC00
Extension Base (Atomic)

Operands

  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x089FFC00 STLRB <Wt>, [<Xn|SP>{, #0}] A64 00 | 0010001 | 0 | 0 | 11111 | 1 | 11111 | Rn | Rt

Description

Store-Release Register Byte stores a byte from a 32-bit register to a memory location. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(8) data;

AccessDescriptor accdesc;
accdesc = CreateAccDescAcqRel(MemOp_STORE, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

address = GenerateAddress(address, 0, accdesc);
data = X[t, 8];
Mem[address, 1, accdesc] = data;