faddp

Vector Floating-Point Add Pairwise

FADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Adds adjacent pairs of float elements.

Details

Adds adjacent pairs of floating-point elements across the two source vectors, placing results in the destination. For example, with 32-bit floats, (Vn[0]+Vn[1]) and (Vm[0]+Vm[1]) are computed and stored. Executes in AArch64 with NEON support; condition flags are not affected. Addition follows IEEE 754 floating-point semantics.

Pseudocode Operation

for i = 0 to num_pairs-1 do
  Vd[2*i] ← Vn[2*i] + Vn[2*i+1]
  Vd[2*i+1] ← Vm[2*i] + Vm[2*i+1]

Example

FADDP v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
1
011100
sz
1
Rm
11010
1
Rn
Rd
 
Format SIMD Three Register
Opcode 0x2E20D400
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5E30D800 FADDP H<d>, <Vn>.2H A64 01 | 0 | 111100 | 0 | 11000 | 01101 | 10 | Rn | Rd
0x7E30D800 FADDP <V><d>, <Vn>.<T> A64 01 | 1 | 111100 | sz | 11000 | 01101 | 10 | Rn | Rd
0x2E401400 FADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 01110 | 0 | 10 | Rm | 00 | 010 | 1 | Rn | Rd
0x2E20D400 FADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 011100 | sz | 1 | Rm | 11010 | 1 | Rn | Rd
0x64108000 FADDP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 01100100 | size | 010 | 00 | 0 | 100 | Pg | Zm | Zdn

Description

Floating-point Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
bits(2*datasize) concat = operand2:operand1;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    if pair then
        element1 = Elem[concat, 2*e, esize];
        element2 = Elem[concat, (2*e)+1, esize];
    else
        element1 = Elem[operand1, e, esize];
        element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);

V[d, datasize] = result;