stp

Store Pair of Registers (64-bit)

STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]

Stores two 64-bit registers.

Details

The Store Pair of Registers instruction stores two 64-bit registers.

Pseudocode Operation

Memory[address] ← Xt2

Example

STP x3, x4, [x1, #16]

Encoding

Binary Layout
10101000
00
0
imm7
Rt2
Rn
Rt1
 
Format Load/Store Pair
Opcode 0xA9000000
Extension Base

Operands

  • Xt1
    First transfer 64-bit register (load/store pair)
  • Xt2
    Second transfer 64-bit register (load/store pair)
  • Xn
    First source / base 64-bit integer register
  • imm
    Signed immediate value