ldrsw

Load Register Signed Word (Literal)

LDRSW <Xt>, <label>

Loads a word from PC-relative address and sign-extends to 64-bits.

Details

Loads a signed word from memory at a PC-relative address (literal) and sign-extends it to 64 bits. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.

Pseudocode Operation

address ← PC + SignExtend(imm19 << 2, 64);
Xt ← SignExtend(Mem[address, 4], 64);

Example

LDRSW x3, label

Encoding

Binary Layout
10
011
0
00
imm19
Rt
 
Format Load Literal
Opcode 0x98000000
Extension Base

Operands

  • Xt
    Transfer 64-bit integer register (load/store)
  • label
    Label

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xB8800400 LDRSW <Xt>, [<Xn|SP>], #<simm> A64 10 | 111 | 0 | 00 | 10 | 0 | imm9 | 01 | Rn | Rt
0xB8800C00 LDRSW <Xt>, [<Xn|SP>, #<simm>]! A64 10 | 111 | 0 | 00 | 10 | 0 | imm9 | 11 | Rn | Rt
0xB9800000 LDRSW <Xt>, [<Xn|SP>{, #<pimm>}] A64 10 | 111 | 0 | 01 | 10 | imm12 | Rn | Rt
0x98000000 LDRSW <Xt>, <label> A64 10 | 011 | 0 | 00 | imm19 | Rt
0xB8A00800 LDRSW <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}] A64 10 | 111 | 0 | 00 | 10 | 1 | Rm | option | S | 10 | Rn | Rt

Description

Load Register Signed Word (literal) calculates an address from the PC value and an immediate offset, loads a word from memory, and writes it to a register. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address = PC64 + offset;
bits(32) data;
boolean privileged = PSTATE.EL != EL0;

AccessDescriptor accdesc = CreateAccDescGPR(MemOp_LOAD, FALSE, privileged, FALSE);
data = Mem[address, 4, accdesc];
X[t, 64] = SignExtend(data, 64);