vcnt

Vector Count Set Bits

VCNT<c>.8 <Qd>, <Qm>

Population count (number of 1s) per byte.

Pseudocode Operation

for i = 0 to 15 do
  count ← 0
  for j = 0 to 7 do
    if (Qm[8*i + j] & (1 << j)) != 0 then
      count ← count + 1
    end if
  end for
  Qd[8*i..8*i+7] ← count
end for

Example

VCNT.8 q0, q2

Encoding

Binary Layout

111100111

31:23

D

22

11

21:20

size

19:18

00

17:16

Vd

15:12

0

11

1010

10:7

0

6

M

5

0

4

Vm

3:0

 

Format NEON 2-Reg

Opcode 0xF3B00500

Extension NEON (SIMD)

Operands

• Qd
  Destination 128-bit SIMD register
• Qm
  Second source 128-bit SIMD register

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xF3B00500	VCNT{<c>}{<q>}.8 <Dd>, <Dm>		A32		111100111 | D | 11 | size | 00 | Vd | 0 | 1010 | 0 | M | 0 | Vm
0xF3B00540	VCNT{<c>}{<q>}.8 <Qd>, <Qm>		A32		111100111 | D | 11 | size | 00 | Vd | 0 | 1010 | 1 | M | 0 | Vm
0xFFB00500	VCNT{<c>}{<q>}.8 <Dd>, <Dm>		T32		111111111 | D | 11 | size | 00 | Vd | 0 | 1010 | 0 | M | 0 | Vm
0xFFB00540	VCNT{<c>}{<q>}.8 <Qd>, <Qm>		T32		111111111 | D | 11 | size | 00 | Vd | 0 | 1010 | 1 | M | 0 | Vm

Description

Vector Count Set Bits counts the number of bits that are one in each element in a vector, and places the results in a second vector. The operand vector elements must be 8-bit fields. The result vector elements are 8-bit integers. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            Elem[D[d+r],e,esize] = BitCount(Elem[D[m+r],e,esize])<esize-1:0>;