ummla

Unsigned Integer Matrix Multiply-Accumulate (NEON)

UMMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Performs 2x2 matrix multiplication on Unsigned Int8 tiles.

Details

Performs a 2×2 unsigned integer matrix multiply-accumulate operation on Int8 tiles, accumulating the result into Int32 elements of the destination vector. Requires FEAT_I8MM. No flags are affected. Operates on 128-bit NEON vectors.

Pseudocode Operation

for i = 0 to 1 do
  for j = 0 to 1 do
    sum ← Vd[i*4+j*4 : i*4+j*4+31]
    for k = 0 to 1 do
      sum ← sum + (ZeroExtend(Vn[i*4+k*4 : i*4+k*4+7]) × ZeroExtend(Vm[k*4+j*4 : k*4+j*4+7]))
    end for
    Vd[i*4+j*4 : i*4+j*4+31] ← sum
  end for
end for

Example

UMMLA v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
1
1
01110
10
0
Rm
1010
0
1
Rn
Rd
 
Format NEON 3-Reg
Opcode 0x6E80A400
Extension FEAT_I8MM (AI)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x6E80A400 UMMLA <Vd>.4S, <Vn>.16B, <Vm>.16B A64 0 | 1 | 1 | 01110 | 10 | 0 | Rm | 1010 | 0 | 1 | Rn | Rd
0x45C09800 UMMLA <Zda>.S, <Zn>.B, <Zm>.B A64 01000101 | 1 | 1 | 0 | Zm | 100110 | Zn | Zda

Description

Unsigned 8-bit integer matrix multiply-accumulate. This instruction multiplies the 2x8 matrix of unsigned 8-bit integer values in the first source vector by the 8x2 matrix of unsigned 8-bit integer values in the second source vector. The resulting 2x2 32-bit integer matrix product is destructively added to the 32-bit integer matrix accumulator in the destination vector. This is equivalent to performing an 8-way dot product per destination element. From Armv8.2 to Armv8.5, this is an OPTIONAL instruction. From Armv8.6 it is mandatory for implementations that include Advanced SIMD to support it. ID_AA64ISAR1_EL1.I8MM indicates whether this instruction is supported.

Operation

CheckFPAdvSIMDEnabled64();
bits(128) operand1 = V[n, 128];
bits(128) operand2 = V[m, 128];
bits(128) addend = V[d, 128];

V[d, 128] = MatMulAdd(addend, operand1, operand2, TRUE, TRUE);