fcmp

Floating-point Compare (Single)

FCMP <Sn>, <Sm>

Compares two single-precision registers and updates NZCV flags.

Details

Compares two single-precision floating-point registers (Sn and Sm) and updates the NZCV condition flags based on the result. Handles NaN operands by setting both N and V flags; neither operand being NaN results in N, Z, C, V being set according to the comparison outcome. AArch64 only.

Pseudocode Operation

op1 ← FPUnpack(Sn)
op2 ← FPUnpack(Sm)
result ← FPCompare(op1, op2)
if isNaN(op1) or isNaN(op2) then
  N ← 1; Z ← 0; C ← 1; V ← 1
else if op1 == op2 then
  N ← 0; Z ← 1; C ← 1; V ← 0
else if op1 < op2 then
  N ← 1; Z ← 0; C ← 0; V ← 0
else
  N ← 0; Z ← 0; C ← 1; V ← 0

Example

FCMP s1, s2

Encoding

Binary Layout
0
0
0
11110
00
1
Rm
00
1000
Rn
00
000
 
Format Float Compare
Opcode 0x1E202000
Extension F.P.

Operands

  • Sn
    First source 32-bit floating-point register
  • Sm
    Second source 32-bit floating-point register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x1EE02000 FCMP <Hn>, <Hm> A64 0 | 0 | 0 | 11110 | 11 | 1 | Rm | 00 | 1000 | Rn | 00 | 000
0x1EE02008 FCMP <Hn>, #0.0 A64 0 | 0 | 0 | 11110 | 11 | 1 | 00000 | 00 | 1000 | Rn | 01 | 000
0x1E202000 FCMP <Sn>, <Sm> A64 0 | 0 | 0 | 11110 | 00 | 1 | Rm | 00 | 1000 | Rn | 00 | 000
0x1E202008 FCMP <Sn>, #0.0 A64 0 | 0 | 0 | 11110 | 00 | 1 | 00000 | 00 | 1000 | Rn | 01 | 000
0x1E602000 FCMP <Dn>, <Dm> A64 0 | 0 | 0 | 11110 | 01 | 1 | Rm | 00 | 1000 | Rn | 00 | 000
0x1E602008 FCMP <Dn>, #0.0 A64 0 | 0 | 0 | 11110 | 01 | 1 | 00000 | 00 | 1000 | Rn | 01 | 000

Description

Floating-point quiet Compare (scalar). This instruction compares the two SIMD&FP source register values, or the first SIMD&FP source register value and zero. It writes the result to the PSTATE.{N, Z, C, V} flags. This instruction raises an Invalid Operation floating-point exception if either or both of the operands is a signaling NaN. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2;

operand2 = if cmp_with_zero then FPZero('0', datasize) else V[m, datasize];

PSTATE.<N,Z,C,V> = FPCompare(operand1, operand2, signal_all_nans, FPCR);