ldnf1h

SVE Load Non-Fault Contiguous Halfwords

LDNF1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>]

Loads halfwords without faulting.

Details

The SVE Load Non-Fault Contiguous Halfwords instruction loads halfwords without faulting.

Pseudocode Operation

// Loads halfwords without faulting

Example

LDNF1H p0/m/Z, [x1]

Encoding

Binary Layout
10100100
01
101000
Pg
Rn
Zt
 
Format SVE Load
Opcode 0xA4680000
Extension SVE

Operands

  • Zt
    Transfer scalable vector register (SVE load/store)
  • Pg
    Predicate
  • Xn
    First source / base 64-bit integer register