ldnf1h

SVE Load Non-Fault Contiguous Halfwords

LDNF1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>]

Loads halfwords without faulting.

Details

Loads halfwords from memory into a scalable vector register without raising faults; elements that would fault are loaded as zero. Only elements where the predicate is true are accessed. This instruction is AArch64-only and requires SVE. No condition flags are set.

Pseudocode Operation

for i ← 0 to (VL/16 - 1) do if Pg[i] then if fault_would_occur then Zt[i*16+15:i*16] ← 0; else Zt[i*16+15:i*16] ← [Xn + i*2]; end if; end if; end for

Example

LDNF1H p0/m/Z, [x1]

Encoding

Binary Layout
1010010
010
1
1
imm4
101
Pg
Rn
Zt
 
Format SVE Load
Opcode 0xA4B0A000
Extension SVE

Operands

  • Zt
    Transfer scalable vector register (SVE load/store)
  • Pg
    Predicate
  • Xn
    First source / base 64-bit integer register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xA4B0A000 LDNF1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 1010010 | 010 | 1 | 1 | imm4 | 101 | Pg | Rn | Zt
0xA4D0A000 LDNF1H { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 1010010 | 011 | 0 | 1 | imm4 | 101 | Pg | Rn | Zt
0xA4F0A000 LDNF1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 1010010 | 011 | 1 | 1 | imm4 | 101 | Pg | Rn | Zt

Description

Contiguous load with non-faulting behavior of unsigned halfwords to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

Operation

CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(64) base;
bits(PL) mask = P[g, PL];
bits(VL) result;
bits(VL) orig = Z[t, VL];
bits(msize) data;
constant integer mbytes = msize DIV 8;
boolean fault = FALSE;
boolean faulted = FALSE;
boolean unknown = FALSE;
boolean contiguous = TRUE;
boolean tagchecked = n != 31;
AccessDescriptor accdesc = CreateAccDescSVENF(contiguous, tagchecked);

if !AnyActiveElement(mask, esize) then
    if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then
        CheckSPAlignment();
else
    if n == 31 then CheckSPAlignment();
    base = if n == 31 then SP[] else X[n, 64];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        integer eoff = (offset * elements) + e;
        bits(64) addr = GenerateAddress(base, eoff * mbytes, accdesc);
        // MemNF[] will return fault=TRUE if access is not performed for any reason
        (data, fault) = MemNF[addr, mbytes, accdesc];
    else
        (data, fault) = (Zeros(msize), FALSE);

    // FFR elements set to FALSE following a suppressed access/fault
    faulted = faulted || fault;
    if faulted then
        ElemFFR[e, esize] = '0';

    // Value becomes CONSTRAINED UNPREDICTABLE after an FFR element is FALSE
    unknown = unknown || ElemFFR[e, esize] == '0';
    if unknown then
        if !fault && ConstrainUnpredictableBool(Unpredictable_SVELDNFDATA) then
            Elem[result, e, esize] = Extend(data, esize, unsigned);
        elsif ConstrainUnpredictableBool(Unpredictable_SVELDNFZERO) then
            Elem[result, e, esize] = Zeros(esize);
        else  // merge
            Elem[result, e, esize] = Elem[orig, e, esize];
    else
        Elem[result, e, esize] = Extend(data, esize, unsigned);

Z[t, VL] = result;