vext

Vector Extract

VEXT<c>.8 <Qd>, <Qn>, <Qm>, #<imm>

Extracts a new vector from a pair of vectors (Sliding window).

Details

Extracts a contiguous sequence of bytes from the concatenation of two 128-bit NEON vectors and stores the result in the destination. The vectors Qn and Qm are logically concatenated, then bytes [imm:imm+15] are extracted to form Qd. All operations are on 8-bit granularity. No condition flags are affected. This is an ARMv7 Advanced SIMD instruction, executable in both A32 and T32 states.

Pseudocode Operation

combined ← (Qn << (imm * 8)) | (Qm >> ((16 - imm) * 8))
Qd ← combined[127:0]
for i = 0 to 15
  Qd[8*i+7:8*i] ← (Qn || Qm)[8*(imm+i)+7:8*(imm+i)]

Example

VEXT.8 q0, q1, q2, #16

Encoding

Binary Layout
111100101
D
11
Vn
Vd
imm4
N
0
M
0
Vm
 
Format NEON Extract
Opcode 0xF2B00000
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    Low Src
  • Qm
    High Src
  • imm
    Byte Offset

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2B00000 VEXT{<c>}{<q>}.8 {<Dd>,} <Dn>, <Dm>, #<imm> A32 111100101 | D | 11 | Vn | Vd | imm4 | N | 0 | M | 0 | Vm
0xF2B00040 VEXT{<c>}{<q>}.8 {<Qd>,} <Qn>, <Qm>, #<imm> A32 111100101 | D | 11 | Vn | Vd | imm4 | N | 1 | M | 0 | Vm
0xEFB00000 VEXT{<c>}{<q>}.8 {<Dd>,} <Dn>, <Dm>, #<imm> T32 111011111 | D | 11 | Vn | Vd | imm4 | N | 0 | M | 0 | Vm
0xEFB00040 VEXT{<c>}{<q>}.8 {<Qd>,} <Qn>, <Qm>, #<imm> T32 111011111 | D | 11 | Vn | Vd | imm4 | N | 1 | M | 0 | Vm
0xF2B00000 VEXT{<c>}{<q>}.<size> {<Dd>,} <Dn>, <Dm>, #<imm> A32 111100101 | D | 11 | Vn | Vd | imm4 | N | 0 | M | 0 | Vm
0xF2B00040 VEXT{<c>}{<q>}.<size> {<Qd>,} <Qn>, <Qm>, #<imm> A32 111100101 | D | 11 | Vn | Vd | imm4 | N | 1 | M | 0 | Vm
0xEFB00000 VEXT{<c>}{<q>}.<size> {<Dd>,} <Dn>, <Dm>, #<imm> T32 111011111 | D | 11 | Vn | Vd | imm4 | N | 0 | M | 0 | Vm
0xEFB00040 VEXT{<c>}{<q>}.<size> {<Qd>,} <Qn>, <Qm>, #<imm> T32 111011111 | D | 11 | Vn | Vd | imm4 | N | 1 | M | 0 | Vm

Description

Vector Extract extracts elements from the bottom end of the second operand vector and the top end of the first, concatenates them and places the result in the destination vector. The elements of the vectors are treated as being 8-bit fields. There is no distinction between data types. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    if quadword_operation then
        Q[d>>1] = (Q[m>>1]:Q[n>>1])<position+127:position>;
    else
        D[d] = (D[m]:D[n])<position+63:position>;